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21. 发明授权

US07652332B2 Extremely-thin silicon-on-insulator transistor with raised source/drain 有权
标题翻译：极薄的绝缘体上硅晶体管，具有升高的源极/漏极
公开(公告)号：US07652332B2
公开(公告)日：2010-01-26
申请号：US11837057
申请日：2007-08-10
申请人： Eduard A. Cartier , Steven J. Koester , Kingsuk Maitra , Amlan Majumdar , Renee T. Mo
发明人： Eduard A. Cartier , Steven J. Koester , Kingsuk Maitra , Amlan Majumdar , Renee T. Mo
IPC分类号： H01L27/01
CPC分类号： H01L29/6659 , H01L21/28079 , H01L29/4958 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6656 , H01L29/66628 , H01L29/66772 , H01L29/78696
摘要： An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.
摘要翻译：提供了一种极薄的绝缘体上硅晶体管，其包括衬底上的掩埋氧化物层，掩埋氧化物层上方的硅层，硅层上的栅极堆叠，硅层上的氮化物衬垫，栅堆叠，氮化物衬垫上并与其相邻的氧化物衬垫，以及升高的源/漏区。栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。凸起的源极/漏极区域中的每一个具有包括硅层的一部分的第一部分，与氧化物衬垫和氮化物衬垫的部分相邻的第二部分，以及在第二部分上方的第三部分。还提供了制造极薄的绝缘体上硅晶体管的方法。

22. 发明申请

US20090283496A1 DIRECTING CARBON NANOTUBE GROWTH 有权
标题翻译：指导碳纳米管生长
公开(公告)号：US20090283496A1
公开(公告)日：2009-11-19
申请号：US11391920
申请日：2006-03-28
申请人： Marko Radosavljevic , Jack T. Kavalieros , Amlan Majumdar , Suman Datta
发明人： Marko Radosavljevic , Jack T. Kavalieros , Amlan Majumdar , Suman Datta
IPC分类号： B44C1/22 , B05D5/12
CPC分类号： B82Y40/00 , B82Y30/00 , C01B32/162
摘要： Embodiments of the invention include apparatuses and methods relating to directed carbon nanotube growth using a patterned layer. In some embodiments, the patterned layer includes an inhibitor material that directs the growth of carbon nanotubes.
摘要翻译：本发明的实施例包括与使用图案化层的定向碳纳米管生长相关的装置和方法。在一些实施方案中，图案化层包括引导碳纳米管生长的抑制剂材料。

23. 发明申请

US20090108314A1 Embedded DRAM Integrated Circuits With Extremely Thin Silicon-On-Insulator Pass Transistors 有权
标题翻译：嵌入式DRAM集成电路与极薄的绝缘体上硅晶体管
公开(公告)号：US20090108314A1
公开(公告)日：2009-04-30
申请号：US11929943
申请日：2007-10-30
申请人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
发明人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10894
摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
摘要翻译：提供具有组合的存储器和逻辑功能的集成电路。一方面，提供集成电路。集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

24. 发明申请

US20080308867A1 PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION 有权
标题翻译：具有金属化源侧HALO区域的部分沉积SOI场效应晶体管
公开(公告)号：US20080308867A1
公开(公告)日：2008-12-18
申请号：US11761568
申请日：2007-06-12
申请人： Jin Cai , Wilfried Haensch , Amlan Majumdar
发明人： Jin Cai , Wilfried Haensch , Amlan Majumdar
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/458 , H01L29/66772 , H01L29/78612 , H01L29/78624
摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.
摘要翻译：源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

25. 发明申请

US20080237573A1 Mechanism for forming a remote delta doping layer of a quantum well structure 有权
标题翻译：用于形成量子阱结构的远程δ掺杂层的机理
公开(公告)号：US20080237573A1
公开(公告)日：2008-10-02
申请号：US11731266
申请日：2007-03-29
申请人： Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Amlan Majumdar , Roberts S. Chau
发明人： Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Amlan Majumdar , Roberts S. Chau
IPC分类号： H01L29/06
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译：制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。

26. 发明授权

US07279375B2 Block contact architectures for nanoscale channel transistors 有权
公开(公告)号：US07279375B2
公开(公告)日：2007-10-09
申请号：US11173866
申请日：2005-06-30
申请人： Marko Radosavljevic , Amlan Majumdar , Brian S. Doyle , Jack Kavalieros , Mark L. Doczy , Justin K. Brask , Uday Shah , Suman Datta , Robert S. Chau
发明人： Marko Radosavljevic , Amlan Majumdar , Brian S. Doyle , Jack Kavalieros , Mark L. Doczy , Justin K. Brask , Uday Shah , Suman Datta , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/7851 , H01L29/78681 , H01L29/78684 , H01L2029/7858
摘要： A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

27. 发明申请

US20070152266A1 Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers 审中-公开
标题翻译：通过使用外延层减小三维晶体管的外部电阻的方法和结构
公开(公告)号：US20070152266A1
公开(公告)日：2007-07-05
申请号：US11322795
申请日：2005-12-29
申请人： Brian Doyle , Justin Brask , Amlan Majumdar , Suman Datta , Jack Kavalieros , Marko Radosavljevic , Robert Chau
发明人： Brian Doyle , Justin Brask , Amlan Majumdar , Suman Datta , Jack Kavalieros , Marko Radosavljevic , Robert Chau
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66628 , H01L29/66795 , H01L29/7848
摘要： The fabrication of a tri-gate transistor formed with a replacement gate process is described. A nitride dummy gate, in one embodiment, is used allowing the growth of epitaxial source and drain regions immediately adjacent to the dummy gate. This reduces the external resistance.
摘要翻译：描述了用替换栅极工艺形成的三栅极晶体管的制造。在一个实施例中，使用氮化物虚拟栅极，允许生长与伪栅极紧邻的外延源极和漏极区域。这减少了外部电阻。

28. 发明申请

US20070145468A1 Quantum dot nonvolatile transistor 审中-公开
标题翻译：量子点非易失性晶体管
公开(公告)号：US20070145468A1
公开(公告)日：2007-06-28
申请号：US11322089
申请日：2005-12-28
申请人： Amlan Majumdar , Suman Datta , Been-Yih Jin , Mark Doczy , Robert Chau
发明人： Amlan Majumdar , Suman Datta , Been-Yih Jin , Mark Doczy , Robert Chau
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , B82Y10/00 , H01L27/115 , H01L29/40114 , H01L29/42332 , H01L29/66825
摘要： Some embodiments of the present invention include apparatuses and methods relating to nonvolatile memory transistors.
摘要翻译：本发明的一些实施例包括与非易失性存储晶体管相关的装置和方法。

29. 发明申请

US20070114593A1 Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric 有权
标题翻译：用于在其栅极电介质中具有碳纳米管通道和电浮置量子点的非易失性存储器件的晶体管
公开(公告)号：US20070114593A1
公开(公告)日：2007-05-24
申请号：US11285763
申请日：2005-11-21
申请人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Justin Brask , Brian Doyle , Robert Chau
发明人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Justin Brask , Brian Doyle , Robert Chau
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L29/78696 , H01L51/0048 , H01L51/0541
摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.
摘要翻译：描述了具有源电极和漏电极的晶体管。晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。

30. 发明申请

US20070001173A1 Semiconductor device structures and methods of forming semiconductor structures 有权
标题翻译：半导体器件结构和形成半导体结构的方法
公开(公告)号：US20070001173A1
公开(公告)日：2007-01-04
申请号：US11158661
申请日：2005-06-21
申请人： Justin Brask , Jack Kavalieros , Uday Shah , Suman Datta , Amlan Majumdar , Robert Chau , Brian Doyle
发明人： Justin Brask , Jack Kavalieros , Uday Shah , Suman Datta , Amlan Majumdar , Robert Chau , Brian Doyle
IPC分类号： H01L29/10
CPC分类号： H01L29/7853 , H01L21/30608 , H01L21/30617 , H01L21/3085 , H01L21/84 , H01L29/04 , H01L29/045 , H01L29/0657 , H01L29/51 , H01L29/66795 , H01L29/78681 , H01L29/78684
摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
摘要翻译：对半导体膜的图案化方法进行说明。根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密并且其中所述硬掩模形成在所述第二晶体平面上。接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

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