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21. 发明申请

US20090242955A1 Integrated Circuit, Memory Device and Methods of Manufacturing the Same 审中-公开
标题翻译：集成电路，存储器件及其制造方法
公开(公告)号：US20090242955A1
公开(公告)日：2009-10-01
申请号：US12059469
申请日：2008-03-31
申请人： Dominik Olligs
发明人： Dominik Olligs
IPC分类号： H01L29/788 , H01L21/336 , H01L27/115 , H01L21/8247
CPC分类号： H01L27/11524 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： An integrated circuit includes: a contact structure with a first stack of at least two conductive layers, and a gate electrode with a second stack of conductive layers, the second stack of layers having the same sequence of conductive layers as the first stack.
摘要翻译：集成电路包括：具有至少两个导电层的第一堆叠的接触结构，以及具有第二层导电层的栅电极，所述第二层叠层具有与第一堆叠相同的导电层序列。

22. 发明授权

US07589019B2 Memory cell array and method of forming a memory cell array 有权
标题翻译：存储单元阵列和形成存储单元阵列的方法
公开(公告)号：US07589019B2
公开(公告)日：2009-09-15
申请号：US11443432
申请日：2006-05-31
申请人： Dominik Olligs , Veronika Polei
发明人： Dominik Olligs , Veronika Polei
IPC分类号： H01L21/44 , H01L29/40
CPC分类号： H01L27/115
摘要： A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor substrate and are accessible by addressing at least a corresponding one of the first conductive lines and at least a corresponding one of the second conductive lines. The memory cell array further includes a plurality of supporting lines, where the supporting lines have a pitch Mp and are disposed above the first and second conductive lines, and a plurality of supporting contacts. The first conductive lines are connected with corresponding ones of the supporting lines via the supporting contacts, and Mp is larger than Bp.
摘要翻译：存储单元阵列包括沿第一方向延伸的多条第一导线，其中第一导线具有间距Bp，多条第二导线和多个存储单元。每个存储单元至少部分地形成在半导体衬底中，并且可以通过寻址至少对应的一个第一导线和至少相应的一个第二导线。存储单元阵列还包括多个支撑线，其中支撑线具有间距Mp并且设置在第一和第二导线上方，以及多个支撑触点。第一导线通过支撑触点与相应的支撑线连接，Mp大于Bp。

23. 发明申请

US20080232170A1 MEMORY DEVICE, A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING A MEMORY DEVICE 有权
标题翻译：存储器件，非易失性半导体存储器件和形成存储器件的方法
公开(公告)号：US20080232170A1
公开(公告)日：2008-09-25
申请号：US11688949
申请日：2007-03-21
申请人： Joachim Deppe , Dominik Olligs , Christoph Kleint , Eike Ruttkowski , Ricardo Mikalo
发明人： Joachim Deppe , Dominik Olligs , Christoph Kleint , Eike Ruttkowski , Ricardo Mikalo
IPC分类号： G11C16/04
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11568 , H01L27/11573
摘要： A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a surface of a semiconductor carrier.
摘要翻译：公开了具有包括存储单元的阵列部分和包括导线的周边部分的存储器件。在一个实施例中，部分导线与半导体载体的表面相邻。

24. 发明授权

US07368350B2 Memory cell arrays and methods for producing memory cell arrays 有权
标题翻译：用于产生存储单元阵列的存储单元阵列和方法
公开(公告)号：US07368350B2
公开(公告)日：2008-05-06
申请号：US11313247
申请日：2005-12-20
申请人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
发明人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/76831 , H01L21/76888 , H01L21/76897 , H01L27/11568
摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.
摘要翻译：公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。

25. 发明授权

US07320934B2 Method of forming a contact in a flash memory device 有权
标题翻译：在闪速存储器件中形成触点的方法
公开(公告)号：US07320934B2
公开(公告)日：2008-01-22
申请号：US11157143
申请日：2005-06-20
申请人： Nicolas Nagel , Dominik Olligs
发明人： Nicolas Nagel , Dominik Olligs
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L21/76802 , H01L21/76895 , H01L27/11568
摘要： A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric layer. The hard mask layer may be composed of a material that has an etch resistance as compared to the interlayer dielectric material, e.g., nitride. Openings in the hard mask define positions for the contacts to the local interconnects exposed in the top section.
摘要翻译：在闪速存储器件中形成位线和局部互连之间的接触的方法包括在沉积氧化物介电层之前在平坦化表面上形成硬掩模层，其包括局部互连的暴露的顶部部分。硬掩模层可以由与层间电介质材料（例如氮化物）相比具有耐蚀刻性的材料构成。硬掩模中的开口定义了与顶部暴露的局部互连的触点的位置。

26. 发明申请

US20070278546A1 Memory cell array and method of forming a memory cell array 有权
标题翻译：存储单元阵列和形成存储单元阵列的方法
公开(公告)号：US20070278546A1
公开(公告)日：2007-12-06
申请号：US11443432
申请日：2006-05-31
申请人： Dominik Olligs , Veronika Polei
发明人： Dominik Olligs , Veronika Polei
IPC分类号： H01L29/94
CPC分类号： H01L27/115
摘要： A memory cell array includes a plurality of first conductive lines running in a first direction, where the first conductive lines have a pitch Bp, a plurality of second conductive lines, and a plurality of memory cells. Each of the memory cells are at least partially formed in a semiconductor substrate and are accessible by addressing at least a corresponding one of the first conductive lines and at least a corresponding one of the second conductive lines. The memory cell array further includes a plurality of supporting lines, where the supporting lines have a pitch Mp and are disposed above the first and second conductive lines, and a plurality of supporting contacts. The first conductive lines are connected with corresponding ones of the supporting lines via the supporting contacts, and Mp is larger than Bp.
摘要翻译：存储单元阵列包括沿第一方向延伸的多条第一导线，其中第一导线具有间距Bp，多条第二导线和多个存储单元。每个存储单元至少部分地形成在半导体衬底中，并且可以通过寻址至少对应的一个第一导线和至少相应的一个第二导线。存储单元阵列还包括多个支撑线，其中支撑线具有间距Mp并且设置在第一和第二导线上方，以及多个支撑触点。第一导线通过支撑触点与相应的支撑线连接，Mp大于Bp。

27. 发明申请

US20070238240A1 Method of forming a transistor in a non-volatile memory device 审中-公开
标题翻译：在非易失性存储器件中形成晶体管的方法
公开(公告)号：US20070238240A1
公开(公告)日：2007-10-11
申请号：US11392240
申请日：2006-03-29
申请人： Dominik Olligs , Florian Beug , Ricardo Mikalo
发明人： Dominik Olligs , Florian Beug , Ricardo Mikalo
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L27/11568
摘要： A field-effect transistor is formed that has spacers formed by etching openings into a conductive layer and filling the openings with spacer material. The openings are formed together with a gate web in the conductive layer, wherein the gate web is surrounded by the openings on at least two sides. The spacers serve to define lightly doped drain regions arranged in the underlying substrate between a highly doped drain region and a channel region of the transistor. The transistor thus formed is specifically suited for providing high-voltage currents to memory cells of a non-volatile memory array.
摘要翻译：形成场效应晶体管，其具有通过将开口蚀刻到导电层中并用间隔物材料填充开口而形成的间隔物。开口与导电层中的栅极网一起形成，其中栅极网在至少两侧上由开口包围。间隔物用于限定在高掺杂漏极区域和晶体管的沟道区域之间布置在下面的衬底中的轻掺杂漏极区域。这样形成的晶体管特别适于向非易失性存储器阵列的存储单元提供高电压电流。

28. 发明申请

US20070200149A1 Semiconductor device and method of production 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070200149A1
公开(公告)日：2007-08-30
申请号：US11364586
申请日：2006-02-28
申请人： Veronika Polei , Dominik Olligs
发明人： Veronika Polei , Dominik Olligs
IPC分类号： H01L29/80
CPC分类号： H01L21/0206 , H01L21/28061 , H01L21/32139 , H01L29/4941
摘要： A layer sequence with lateral boundaries, especially a gate electrode stack, comprises a cover layer between a metal layer and a top layer that is provided as a hardmask. The cover layer, which is preferably polysilicon, enables the application of a cleaning agent to remove a resist layer, clean the hardmask and remove deposits of the material of the top layer produced in the structuring of the hardmask, before the layer sequence is structured using the hardmask. The cover layer protects the metal layer, which could otherwise be damaged by the cleaning agent.
摘要翻译：具有横向边界的层序列，特别是栅极电极堆叠，包括在作为硬掩模提供的金属层和顶层之间的覆盖层。优选多晶硅的覆盖层能够在层序列结构化之前使用清洁剂去除抗蚀剂层，清洁硬掩模并去除硬质掩模的结构中产生的顶层材料的沉积物硬掩模覆盖层保护金属层，否则可能由清洁剂损坏。

29. 发明申请

US20070141799A1 Memory cell arrays and methods for producing memory cell arrays 有权
标题翻译：用于产生存储单元阵列的存储单元阵列和方法
公开(公告)号：US20070141799A1
公开(公告)日：2007-06-21
申请号：US11313247
申请日：2005-12-20
申请人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
发明人： Dominik Olligs , Torsten Mueller , Karl-Heinz Kuesters , Veronika Polei , Thomas Mikolajick , Josef Willer
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L21/76831 , H01L21/76888 , H01L21/76897 , H01L27/11568
摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.
摘要翻译：公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。

30. 发明申请

US20070075381A1 Semiconductor memory device and method of production 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070075381A1
公开(公告)日：2007-04-05
申请号：US11241878
申请日：2005-09-30
申请人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
发明人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.
摘要翻译：位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。在阻塞区域之间，字线正常布置在位线上。

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