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21. 发明申请

US20090283859A1 Integrated Circuit Arrangements With ESD-Resistant Capacitor and Corresponding Method of Production 审中-公开
公开(公告)号：US20090283859A1
公开(公告)日：2009-11-19
申请号：US12511835
申请日：2009-07-29
申请人： Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
发明人： Kai Esmark , Harald Gossner , Christian Russ , Jens Schneider
IPC分类号： H01L27/06 , H01L21/768
CPC分类号： H01L29/94 , H01L27/0811
摘要： A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.

22. 发明申请

US20070165344A1 Esd test arrangement and method 有权
标题翻译： Esd测试方法和方法
公开(公告)号：US20070165344A1
公开(公告)日：2007-07-19
申请号：US10569986
申请日：2005-03-17
申请人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
发明人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
IPC分类号： H02H9/00
CPC分类号： G06F17/5036
摘要： The invention relates to a program-controlled arrangement and a method for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit, having a pre-processor, which processes first data about the description of the integrated circuit, second data about already ESD-characterized circuit parts of the integrated circuit, and third data which contain information about ESD test standards, having a simulator device connected downstream of the pre-processor, which has a simulator which, by using the fourth and fifth data generated by the pre-processor, performs an ESD simulation of the integrated circuit, which has a monitoring controller for controlling the ESD simulation sequence in the simulator, having an analysis device connected downstream of the simulator device, which performs an evaluation of the sixth data generated in the simulator device with regard to their physical validity and meaningfulness, and marks the simulation runs having physically relevant ESD failure events.
摘要翻译：本发明涉及一种用于在集成电路的设计或概念中识别ESD和/或闭锁弱点的程序控制布置和方法，所述集成电路具有预处理器，所述预处理器处理关于描述的第一数据集成电路的已经具有ESD特征的电路部分的第二数据以及包含关于ESD测试标准的信息的第三数据，具有连接在预处理器下游的模拟器装置，模拟器装置具有通过使用的模拟器由预处理器生成的第四和第五数据执行集成电路的ESD仿真，其具有用于控制模拟器中的ESD模拟序列的监视控制器，具有连接在模拟器装置的下游的分析装置，该分析装置执行对模拟器装置中生成的第六个数据的物理有效性和有意义进行评估，并标记模拟运行导致身体相关的ESD故障事件。

23. 发明授权

US07087938B2 ESD protective circuit with collector-current-controlled triggering for a monolithically integrated circuit 有权
标题翻译：具有集电极电流控制触发的ESD保护电路用于单片集成电路
公开(公告)号：US07087938B2
公开(公告)日：2006-08-08
申请号：US11070824
申请日：2005-03-01
申请人： Martin Streibl , Kai Esmark , Christian Russ , Martin Wendel , Harald Gossner
发明人： Martin Streibl , Kai Esmark , Christian Russ , Martin Wendel , Harald Gossner
IPC分类号： H01L29/72 , H02H3/00
CPC分类号： H01L27/0262 , H01L27/0259
摘要： An ESD protective circuit protects an input or output of a monolithically integrated circuit. The ESD protective circuit has at least one bipolar transistor structure and one ESD protective element between two supply networks. The emitter of the bipolar transistor structure is electrically connected to the input or output, while the base is electrically connected to one of the two supply networks. The collector produces a current signal, which is used for triggering of the ESD protective element, when an ESD load occurs at the input or output.
摘要翻译： ESD保护电路保护单片集成电路的输入或输出。 ESD保护电路在两个供电网络之间具有至少一个双极晶体管结构和一个ESD保护元件。双极晶体管结构的发射极电连接到输入或输出，而基极电连接到两个供电网络之一。当输入或输出发生ESD负载时，集电极产生电流信号，用于触发ESD保护元件。

24. 发明授权

US08471292B2 Semiconductor ESD device and method of making same 有权
标题翻译：半导体ESD器件及其制造方法
公开(公告)号：US08471292B2
公开(公告)日：2013-06-25
申请号：US13464464
申请日：2012-05-04
申请人： Krzysztof Domanski , Cornelius Christian Russ , Kai Esmark
发明人： Krzysztof Domanski , Cornelius Christian Russ , Kai Esmark
IPC分类号： H01L29/66 , H01L23/62
CPC分类号： H01L27/0262 , H01L21/82 , H01L27/0248 , H01L27/0255 , H01L27/0259 , H01L29/74 , H01L29/7436 , H01L2924/13034
摘要： A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
摘要翻译：半导体器件包括设置在半导体本体内的SCR ESD器件区域，以及设置在第二导电类型的第二器件区域上的第一导电类型的多个第一器件区域，其中第二导电类型与第一导电类型相反。还包括具有第一导电类型的子区域和设置在第二器件区域上的第二导电类型的子区域的多个第三器件区域。第一区域和第二区域分布成使得第三区域不直接相邻。还包括与第二器件区域相邻的第一导电类型的第四器件区域和布置在第四器件区域内的第二导电类型的第五器件区域。

25. 发明授权

US07985983B2 Semiconductor ESD device and method of making same 有权
标题翻译：半导体ESD器件及其制造方法
公开(公告)号：US07985983B2
公开(公告)日：2011-07-26
申请号：US12769021
申请日：2010-04-28
申请人： Cornelius Christian Russ , Kai Esmark , David Alvarez , Jens Schneider
发明人： Cornelius Christian Russ , Kai Esmark , David Alvarez , Jens Schneider
IPC分类号： H01L29/74 , H01L27/06
CPC分类号： H01L29/735 , H01L27/0262 , H01L29/0615 , H01L29/0619 , H01L29/0692 , H01L29/41708 , H01L29/456 , H01L29/732 , H01L29/7436
摘要： A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.
摘要翻译：半导体器件包括设置在第一半导体类型的半导体本体内的ESD器件区域，围绕ESD器件区域的隔离区域，设置在ESD区域内的半导体本体的表面处的第二导电类型的第一掺杂区域，以及设置在ESD区域内的半导体本体与第一掺杂区域的至少一部分之间的第一导电类型的第二掺杂区域，其中第二掺杂区域的掺杂浓度高于半导体本体。第二半导体类型的第三掺杂区域设置在半导体本体上，并且第一导电类型的第四区域设置在第三掺杂区域上。第二导电类型的第五掺杂区域设置在半导体本体上。触发装置和SCR由其形成。

26. 发明授权

US07279726B2 ESD protection device 有权
标题翻译： ESD保护装置
公开(公告)号：US07279726B2
公开(公告)日：2007-10-09
申请号：US11411403
申请日：2006-04-26
申请人： Kai Esmark , Ulrich Glaser , Martin Streibl
发明人： Kai Esmark , Ulrich Glaser , Martin Streibl
IPC分类号： H01L29/00 , H02H3/22
CPC分类号： H01L27/0255
摘要： An ESD protection device for protecting a circuit against electrostatic discharges. The ESD protection device having a series circuit of N diodes, each diode comprising an anode and a cathode. The series circuit being connected between two supply potentials. The diodes being so arranged that a spatial distance between the anode of a first diode and the cathode of an Nth diode of the series circuit is less than a maximum distance between the anode or cathode of a first spatially outer diode of the series circuit and the anode or cathode of a second spatially outer diode of the series circuit.
摘要翻译：一种用于保护电路免受静电放电的ESD保护装置。该ESD保护装置具有N个二极管的串联电路，每个二极管包括阳极和阴极。串联电路连接在两个电源之间。二极管被布置成使得第一二极管的阳极与串联电路的第N个二极管的阴极之间的空间距离小于串联电路的第一空间外部二极管的阳极或阴极之间的最大距离，串联电路的第二空间外部二极管的阳极或阴极。

27. 发明申请

US20120218671A1 Semiconductor ESD Device and Method of Making Same 有权
标题翻译：半导体ESD器件及其制造方法
公开(公告)号：US20120218671A1
公开(公告)日：2012-08-30
申请号：US13464464
申请日：2012-05-04
申请人： Krzysztof Domanski , Cornelius Christian Russ , Kai Esmark
发明人： Krzysztof Domanski , Cornelius Christian Russ , Kai Esmark
IPC分类号： H02H9/04 , H01L21/331
CPC分类号： H01L27/0262 , H01L21/82 , H01L27/0248 , H01L27/0255 , H01L27/0259 , H01L29/74 , H01L29/7436 , H01L2924/13034
摘要： A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
摘要翻译：半导体器件包括设置在半导体本体内的SCR ESD器件区域，以及设置在第二导电类型的第二器件区域上的第一导电类型的多个第一器件区域，其中第二导电类型与第一导电类型相反。还包括具有第一导电类型的子区域和设置在第二器件区域上的第二导电类型的子区域的多个第三器件区域。第一区域和第二区域分布成使得第三区域不直接相邻。还包括与第二器件区域相邻的第一导电类型的第四器件区域和布置在第四器件区域内的第二导电类型的第五器件区域。

28. 发明授权

US07800128B2 Semiconductor ESD device and method of making same 有权
标题翻译：半导体ESD器件及其制造方法
公开(公告)号：US07800128B2
公开(公告)日：2010-09-21
申请号：US12138208
申请日：2008-06-12
申请人： Krzysztof Domanski , Cornelius Christian Russ , Kai Esmark
发明人： Krzysztof Domanski , Cornelius Christian Russ , Kai Esmark
IPC分类号： H01L29/72 , H01L29/74 , H01L27/01 , H01L27/12
CPC分类号： H01L27/0262 , H01L21/82 , H01L27/0248 , H01L27/0255 , H01L27/0259 , H01L29/74 , H01L29/7436 , H01L2924/13034
摘要： A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
摘要翻译：半导体器件包括设置在半导体本体内的SCR ESD器件区域，以及设置在第二导电类型的第二器件区域上的第一导电类型的多个第一器件区域，其中第二导电类型与第一导电类型相反。还包括具有第一导电类型的子区域和设置在第二器件区域上的第二导电类型的子区域的多个第三器件区域。第一区域和第二区域分布成使得第三区域不直接相邻。还包括与第二器件区域相邻的第一导电类型的第四器件区域和布置在第四器件区域内的第二导电类型的第五器件区域。

29. 发明申请

US20050263817A1 Transistor comprising fill areas in the source drain and/or drain region 审中-公开
标题翻译：晶体管包括源极漏极和/或漏极区域中的填充区域
公开(公告)号：US20050263817A1
公开(公告)日：2005-12-01
申请号：US11138918
申请日：2005-05-26
申请人： Martin Wendel , Martin Streibl , Kai Esmark , Philipp Riess , Thomas Schafbauer
发明人： Martin Wendel , Martin Streibl , Kai Esmark , Philipp Riess , Thomas Schafbauer
IPC分类号： H01L29/06 , H01L29/08 , H01L29/78 , H01L29/76
CPC分类号： H01L29/0847 , H01L29/0646 , H01L29/0653 , H01L29/78
摘要： A transistor contains a source region and a drain region. Two or more fill areas are formed such that the fill areas and the source and/or drain region engage in one another. The fill areas have vertical dimensions which are at least of equal size to the vertical dimensions of the source and/or of the drain region. The fill areas and the source and/or drain region extend at least partially over a common vertical section. The fill areas are formed from an oxide and/or a nitride.
摘要翻译：晶体管包含源极区和漏极区。形成两个或更多个填充区域，使得填充区域和源极和/或漏极区域彼此接合。填充区具有与源极和/或漏极区域的垂直尺寸至少相等的垂直尺寸。填充区域和源极和/或漏极区域至少部分地延伸在共同的垂直部分上。填充区域由氧化物和/或氮化物形成。

30. 发明申请

US20130122677A1 Methods of Forming Electrostatic Discharge Devices 有权
标题翻译：形成静电放电装置的方法
公开(公告)号：US20130122677A1
公开(公告)日：2013-05-16
申请号：US13732196
申请日：2012-12-31
申请人： Kai Esmark
发明人： Kai Esmark
IPC分类号： H01L29/66
CPC分类号： H01L29/66234 , H01L23/60 , H01L27/0259 , H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： Electrostatic discharge devices and methods of forming thereof are disclosed. In one embodiment, a semiconductor device includes an electrostatic discharge (ESD) device region disposed within a semiconductor body. A first ESD device is disposed in a first region of the ESD device region, and a second ESD device disposed in a second region of the ESD device region. The second region is separated from the first region by a first trench.
摘要翻译：公开了静电放电装置及其形成方法。在一个实施例中，半导体器件包括设置在半导体本体内的静电放电（ESD）器件区域。第一ESD器件设置在ESD器件区域的第一区域中，以及设置在ESD器件区域的第二区域中的第二ESD器件。第二区域通过第一沟槽与第一区域分离。

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