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21. 发明申请

US20140082252A1 Combined Two-Level Cache Directory 审中-公开
标题翻译：组合二级缓存目录
公开(公告)号：US20140082252A1
公开(公告)日：2014-03-20
申请号：US13621465
申请日：2012-09-17
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Barry W. Krumm
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Barry W. Krumm
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0811 , G06F12/1054
摘要： Responsive to receiving a logical address for a cache access, a mechanism looks up a first portion of the logical address in a local cache directory for a local cache. The local cache directory returns a set identifier for each set in the local cache directory. Each set identifier indicates a set within a higher level cache directory. The mechanism looks up a second portion of the logical address in the higher level cache directory and compares each absolute address value received from the higher level cache directory to an absolute address received from a translation look-aside buffer to generate a higher level cache hit signal. The mechanism compares the higher level cache hit signal to each set identifier to generate a local cache hit signal and responsive to the local cache hit signal indicating a local cache hit, accesses the local cache based on the local cache hit signal.
摘要翻译：响应于接收高速缓存访问的逻辑地址，机制在本地高速缓存目录中查找本地高速缓存的逻辑地址的第一部分。本地缓存目录返回本地缓存目录中每个集合的集合标识符。每个集合标识符表示较高级别的高速缓存目录中的集合。该机制查找较高级别高速缓存目录中的逻辑地址的第二部分，并将从较高级别高速缓存目录接收的每个绝对地址值与从翻译后备缓冲器接收的绝对地址进行比较，以产生更高级别的高速缓存命中信号。该机制将高级缓存命中信号与每个集合标识符进行比较以产生本地高速缓存命中信号，并且响应于指示本地高速缓存命中的本地高速缓存命中信号，基于本地高速缓存命中信号访问本地高速缓存。

22. 发明授权

US09218288B2 Monitoring a value in storage without repeated storage access 有权
标题翻译：在不重复存储访问的情况下监视存储中的值
公开(公告)号：US09218288B2
公开(公告)日：2015-12-22
申请号：US13524063
申请日：2012-06-15
申请人： Khary J. Alexander , Ute Gaertner , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
发明人： Khary J. Alexander , Ute Gaertner , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F12/02 , G06F12/08 , G06F3/06
CPC分类号： G06F12/0808 , G06F3/0653 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit.
摘要翻译：提供了一种用于监视值而不重复存储访问的技术。处理电路处理指定要监视的存储器位置的存储器地址的程序的指令。处理电路配置用于监视存储器位置的监视站。存储器位置包括程序的状态描述符。处理电路从存储器控制器接收到交叉无效请求。交叉无效请求向监视台指示存储器位置的内容已被另一处理电路改变。

23. 发明申请

US20130339628A1 DETERMINING THE LOGICAL ADDRESS OF A TRANSACTION ABORT 有权
标题翻译：确定交易的逻辑地址
公开(公告)号：US20130339628A1
公开(公告)日：2013-12-19
申请号：US13524342
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F12/08 , G06F12/0808 , G06F12/0815 , G06F12/0822 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application. The one or more instructions are executed within a first transaction. The first transaction delays committing stores to memory until it has completed. At least one of the one or more instructions includes a first logical memory address. The first logical memory address corresponds to a first memory address in a memory system. It is determined if the first memory address is equal to a second memory address that is stored in a conflict register. Based on determining that they are equal the first logical memory address is saved as a logical address associated with a cross invalidate (XI) signal at a location available to the application.
摘要翻译：实施例涉及确定事务中止的逻辑地址。在一个实施例中，从应用程序接收一个或多个接收的指令。一个或多个指令在第一事务中执行。第一个交易延迟将存储提交到内存，直到它完成。所述一个或多个指令中的至少一个包括第一逻辑存储器地址。第一逻辑存储器地址对应于存储器系统中的第一存储器地址。确定第一存储器地址是否等于存储在冲突寄存器中的第二存储器地址。基于确定它们相等，第一逻辑存储器地址被保存为与应用可用的位置处的交叉无效（XI）信号相关联的逻辑地址。

24. 发明授权

US09015419B2 Avoiding aborts due to associativity conflicts in a transactional environment 有权
标题翻译：避免由于交易环境中的联系冲突而中断
公开(公告)号：US09015419B2
公开(公告)日：2015-04-21
申请号：US13524378
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
IPC分类号： G06F12/00 , G06F9/46 , G06F12/08
CPC分类号： G06F12/0804 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/467
摘要： Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set.
摘要翻译：实施例涉及缓存线驱逐之后的事务读取占用空间。一个方面包括在活动事务中执行一个或多个读取指令。接收对目标高速缓存行的交叉无效（XI）请求，并且确定目标高速缓存行是否是本地高速缓存中的同余类的一部分。进一步确定是否设置与同余类相关联的扩展标志。扩展标志用于指示仅基于最近最少使用的并且目标高速缓存行不在高速缓存中，与活动事务相关联的一致类的高速缓存行已被替换。基于确定扩展标志未设置，继续执行活动事务。基于确定扩展标志被设置，中止活动事务的执行。

25. 发明申请

US20130339684A1 RESTRICTING PROCESSING WITHIN A PROCESSOR TO FACILITATE TRANSACTION COMPLETION 有权
公开(公告)号：US20130339684A1
公开(公告)日：2013-12-19
申请号：US13524833
申请日：2012-06-15
申请人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
发明人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/38 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/52 , G06F9/524
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

26. 发明申请

US20130339650A1 PREFETCH ADDRESS TRANSLATION USING PREFETCH BUFFER 有权
标题翻译：使用PREFETCH BUFFER的前缀地址翻译
公开(公告)号：US20130339650A1
公开(公告)日：2013-12-19
申请号：US13523919
申请日：2012-06-15
申请人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Christian Jacobi , Shmuel Paycher , Chung-Lung K. Shum
发明人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Christian Jacobi , Shmuel Paycher , Chung-Lung K. Shum
IPC分类号： G06F12/10
CPC分类号： G06F12/0862 , G06F12/1009
摘要： Embodiments relate to prefetch address translation in a computer processor. An aspect includes issuing, by prefetch logic, a prefetch request comprising a virtual page address. Another aspect includes, based on the prefetch request missing the TLB and the address translation logic of the processor being busy performing a current translation request, comparing a page of the prefetch request to a page of the current translation request. Yet another aspect includes, based on the page of the prefetch request matching the page of the current translation request, storing the prefetch request in a prefetch buffer.
摘要翻译：实施例涉及计算机处理器中的预取地址转换。一方面包括通过预取逻辑发出包括虚拟页面地址的预取请求。另一方面包括：基于预取请求，丢失TLB，处理器的地址转换逻辑正在执行当前转换请求，将预取请求的页面与当前转换请求的页面进行比较。另一方面包括：基于与当前转换请求的页面匹配的预取请求的页面，将预取请求存储在预取缓冲器中。

27. 发明申请

US20130339615A1 MANAGING TRANSACTIONAL AND NON-TRANSACTIONAL STORE OBSERVABILITY 有权
标题翻译：管理交易和非交易商店的可观察性
公开(公告)号：US20130339615A1
公开(公告)日：2013-12-19
申请号：US13524386
申请日：2012-06-15
申请人： Khary J. Alexander , Christian Jacobi , Hans-Werner Tast , Patrick M. West
发明人： Khary J. Alexander , Christian Jacobi , Hans-Werner Tast , Patrick M. West
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F9/467 , G06F11/1474 , G06F12/0828
摘要： Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.
摘要翻译：实施例涉及控制事务和非交易存储的可观察性。一方面包括接收一个或多个存储指令。一个或多个存储指令在活动事务中启动并且包括存储数据。活动事务有效地延迟将存储提交到存储器，直到成功完成活动事务。存储数据存储在本地存储缓冲器中，导致本地存储缓冲器从第一状态到第二状态的改变。接收到有效事务终止的信号。如果活动事务已经异常终止，则：如果存储数据由事务存储指令存储，则本地存储缓冲区被恢复到第一状态，并且如果存储指令是非事务性的则将其传播到共享高速缓存。

28. 发明授权

US10437602B2 Program interruption filtering in transactional execution 有权
公开(公告)号：US10437602B2
公开(公告)日：2019-10-08
申请号：US13524839
申请日：2012-06-15
申请人： Dan F. Greiner , Christian Jacobi , Marcel Mitran , Timothy J. Slegel
发明人： Dan F. Greiner , Christian Jacobi , Marcel Mitran , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48
摘要： Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.

29. 发明授权

US09740549B2 Facilitating transaction completion subsequent to repeated aborts of the transaction 有权
公开(公告)号：US09740549B2
公开(公告)日：2017-08-22
申请号：US13524857
申请日：2012-06-15
申请人： Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Timothy J. Slegel
发明人： Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Timothy J. Slegel
IPC分类号： G06F7/00 , G06F17/00 , G06F11/07 , G06F17/30 , G06F9/46 , G06F13/24
CPC分类号： G06F11/076 , G06F9/466 , G06F11/0721 , G06F13/24 , G06F17/30371
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

30. 发明授权

US09710266B2 Instruction to compute the distance to a specified memory boundary 有权
公开(公告)号：US09710266B2
公开(公告)日：2017-07-18
申请号：US13421451
申请日：2012-03-15
申请人： Jonathan D. Bradbury , Michael K. Gschwind , Christian Jacobi , Eric M. Schwarz , Timothy J. Slegel
发明人： Jonathan D. Bradbury , Michael K. Gschwind , Christian Jacobi , Eric M. Schwarz , Timothy J. Slegel
IPC分类号： G06F9/38 , G06F9/30 , G06F9/355
CPC分类号： G06F9/30043 , G06F9/3001 , G06F9/3004 , G06F9/30076 , G06F9/355 , G06F9/3824 , G06F9/3861
摘要： A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.

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