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21. 发明授权

US07123528B2 Flash memory device having column predecoder capable of selecting all column selection transistors and stress test method thereof 有权
标题翻译：具有能够选择所有列选择晶体管的列预解码器的闪存器件及其压力测试方法
公开(公告)号：US07123528B2
公开(公告)日：2006-10-17
申请号：US10677841
申请日：2003-10-01
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C8/12 , G11C16/04 , G11C2029/1204 , G11C2029/2602
摘要： A column predecoder includes a buffer unit for inputting all column selection signals, decoder units for decoding an output of the buffer unit and column addresses, and level shifters for shifting voltage levels of column selection signals coupled to gates of the column selection transistors in response to an output of the decoder units. Since a ground voltage is applied to a bitline and a high voltage is applied to all column selection signals during the stress test, the stress test time can be shortened.
摘要翻译：列预解码器包括用于输入所有列选择信号的缓冲单元，用于对缓冲单元和列地址的输出进行解码的解码器单元和用于响应于列选择晶体管的栅极耦合到列选择晶体管的列选择信号的电压电平的电平移位器解码器单元的输出。由于接地电压施加于位线，并且在应力测试期间对所有列选择信号施加高电压，所以可以缩短应力测试时间。

22. 发明申请

US20060104104A1 Methods for accelerated erase operations in non-volatile memory devices and related devices 失效
标题翻译：在非易失性存储器件和相关器件中加速擦除操作的方法
公开(公告)号：US20060104104A1
公开(公告)日：2006-05-18
申请号：US11247839
申请日：2005-10-11
申请人： Jae-Woo Park , Jae-Yong Jeong
发明人： Jae-Woo Park , Jae-Yong Jeong
IPC分类号： G11C17/00
CPC分类号： G11C16/3468
摘要： Memory cells in a memory cell array are erased using an erase operation followed by a post-program operation. In the erase operation, an erase voltage is applied to a plurality of memory cells of the memory cell array. In the post program operation, a program voltage is simultaneously applied to at least two word lines coupled to ones of the plurality of erased memory cells of the memory cell array. Related devices are also discussed.
摘要翻译：存储单元阵列中的存储单元将使用擦除操作，随后进行后期程序擦除。在擦除操作中，擦除电压被施加到存储单元阵列的多个存储单元。在后期编程操作中，将编程电压同时施加到与存储单元阵列的多个被擦除的存储单元中的一个相连的至少两个字线。还讨论了相关设备。

23. 发明申请

US20060087891A1 Non-volatile memory device and method of programming same 失效
标题翻译：非易失性存储器件和编程方法相同
公开(公告)号：US20060087891A1
公开(公告)日：2006-04-27
申请号：US11257074
申请日：2005-10-25
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/24
摘要： Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.
摘要翻译：公开了一种非易失性存储器件及其编程方法。该方法包括在多个程序循环期间将字线电压，位线电压和体电压施加到存储器单元。在当前程序循环期间位线电压下降到低于第一预定检测电压或体电压变得高于第二预定检测电压的情况下，在当前编程环路中使用相同的字线电压，并在下一个程序循环当前程序循环。否则，在下一个编程循环之前，字线电压增加预定量。

24. 发明申请

US20060067130A1 Nonvolatile memory devices including overlapped data sensing and verification and methods of verifying data in nonvolatile memory devices 有权
标题翻译：包括重叠数据传感和验证的非易失性存储器件以及在非易失性存储器件中验证数据的方法
公开(公告)号：US20060067130A1
公开(公告)日：2006-03-30
申请号：US11017335
申请日：2004-12-20
申请人： Jae-Yong Jeong
发明人： Jae-Yong Jeong
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/3436
摘要： Data verification methods and/or nonvolatile memory devices are provided that concurrently detect data for a selected memory cell of the nonvolatile memory device and verify a programmed or erase state of previously detected data of a different memory cell of the nonvolatile memory device. Concurrently detecting data and verifying a programmed or erase state may be provided by a sense amplifier configured to sense data from a memory cell of the nonvolatile memory device, a latch configured to store the data sensed by the sense amplifier, an I/O buffer configured to store the data stored in the latch and a program/erase verifier circuit configured to control the sense amplifier, latch and I/O buffer to provided previously sensed data for a first memory cell to the program erase/verifier circuit for verification while the sense amplifier is sensing data for a second memory cell.
摘要翻译：提供了数据验证方法和/或非易失性存储器件，其同时检测非易失性存储器件的选定存储单元的数据，并验证非易失性存储器件的不同存储单元的先前检测到的数据的编程或擦除状态。同时检测数据和验证编程或擦除状态可以由配置成感测来自非易失性存储器件的存储单元的数据的读出放大器提供，配置成存储读出放大器检测到的数据的锁存器，配置的I / O缓冲器存储在锁存器中的数据和编程/擦除验证器电路，其被配置为控制读出放大器，锁存器和I / O缓冲器，以将第一存储器单元的先前检测到的数据提供给程序擦除/验证器电路以进行验证放大器感测第二存储单元的数据。

25. 发明授权

US06717861B2 Non-volatile semiconductor memory device capable of preventing program disturb due to noise voltage induced at a string select line and program method thereof 有权
标题翻译：能够防止由串选择线引起的噪声电压引起的程序干扰的非易失性半导体存储装置及其编程方法
公开(公告)号：US06717861B2
公开(公告)日：2004-04-06
申请号：US10006196
申请日：2001-12-04
申请人： Jae-Yong Jeong , Sung-Soo Lee
发明人： Jae-Yong Jeong , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Disclosed is a non-volatile semiconductor memory device including a circuit for controlling potentials of select lines and word lines in accordance with bit line setup, string select line setup, program and discharge periods of a program cycle. The control circuit biases a string select line to a power supply voltage during the bit line setup period in the program cycle, and to a voltage between the power supply voltage and ground voltage during the string select line setup and the program periods. According to the string select line control scheme, program disturb due to a noise voltage induced at a string select line when a program voltage is applied to a word line adjacent to the string select line is prevented.
摘要翻译：公开了一种非易失性半导体存储器件，其包括根据位线设置，串选择线设置，编程周期的编程和放电周期来控制选择线和字线的电位的电路。控制电路在编程周期中的位线建立期间将串选择线偏置为电源电压，并且在串选择线设置和程序周期期间将电源电压和接地电压之间的电压偏置。根据串选择线控制方案，防止当将编程电压施加到与串选择线相邻的字线时在串选择线处感应到的噪声电压时的程序干扰。

26. 发明授权

US06614688B2 Method of programming non-volatile semiconductor memory device 有权
公开(公告)号：US06614688B2
公开(公告)日：2003-09-02
申请号：US09990191
申请日：2001-11-20
申请人： Jae-Yong Jeong , Jin-Seon Yeom , Sung-Soo Lee
发明人： Jae-Yong Jeong , Jin-Seon Yeom , Sung-Soo Lee
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0483
摘要： A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area. In the program step, a program voltage is supplied to selected wordlines and a pass voltage is supplied to unselected wordlines, with the floating second well area biased with the coupling voltage. Therefore, the pocket P-well area is biased with a negative voltage through the capacitance coupling.

27. 发明授权

US06353555B1 Flash memory device capable of minimizing a substrate voltage bouncing and a program method thereof 失效
标题翻译：能够使基板电压反弹最小化的闪存装置及其编程方法
公开(公告)号：US06353555B1
公开(公告)日：2002-03-05
申请号：US09597174
申请日：2000-06-20
申请人： Jae-Yong Jeong
发明人： Jae-Yong Jeong
IPC分类号： G11C1134
CPC分类号： G11C16/08
摘要： Disclosed is a nonvolatile semiconductor memory device which comprises a controller for controlling block select signal generators. The controller simultaneously activates the block select signal generators in a bit line setup and a recovery period, so that the word lines in each of memory blocks are set to a predetermined voltage (for example, a ground voltage, a power supply voltage, or an intermediate voltage), respectively. According to the control scheme, by attenuating a bouncing of a substrate voltage caused in an instant by means of a capacitive coupling between a bit line and a substrate at a transition of a bit line voltage, there are prevented an under program and a program disturb during a program cycle.
摘要翻译：公开了一种非易失性半导体存储器件，其包括用于控制块选择信号发生器的控制器。控制器在位线设置和恢复周期中同时激活块选择信号发生器，使得每个存储器块中的字线被设置为预定电压（例如，接地电压，电源电压或中间电压）。根据该控制方案，通过在位线电压的转变下借助于位线与衬底之间的电容耦合来瞬间引起的衬底电压的跳动，防止了程序和程序干扰在程序周期。

28. 发明授权

US09685206B2 Memory device, memory system, and method of controlling read voltage of the memory device 有权
公开(公告)号：US09685206B2
公开(公告)日：2017-06-20
申请号：US13948557
申请日：2013-07-23
申请人： Myung-Hoon Choi , Jae-Yong Jeong , Ki-Tae Park
发明人： Myung-Hoon Choi , Jae-Yong Jeong , Ki-Tae Park
IPC分类号： G11C7/10 , G11C16/26 , G11C11/56 , G11C16/04 , G11C16/34 , G11C29/44 , G11C29/02 , G11C16/00
CPC分类号： G11C7/1057 , G11C11/5642 , G11C16/00 , G11C16/0483 , G11C16/26 , G11C16/3431 , G11C29/021 , G11C29/028 , G11C29/44
摘要： A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.

29. 发明授权

US08180976B2 Programming non-volatile memory devices based on data logic values 失效
标题翻译：根据数据逻辑值编程非易失性存储器件
公开(公告)号：US08180976B2
公开(公告)日：2012-05-15
申请号：US10982560
申请日：2004-11-05
申请人： Jae-Yong Jeong , Heung-soo Lim
发明人： Jae-Yong Jeong , Heung-soo Lim
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C16/30
摘要： A nonvolatile memory device includes a memory cell array, a data scanning unit, and a program unit. The memory cell array includes a plurality of memory cells, where each of the memory cells is programmable to store data have a first logic value or a second logic value. The data scanning unit is configured to search among a plurality of data to be programmed in the memory cells to identify data having the second logic value. The program unit is configured to group the identified data having the second logic value, and to program at least a portion of the group of identified data at a same time into the memory cells.
摘要翻译：非易失性存储器件包括存储单元阵列，数据扫描单元和程序单元。存储单元阵列包括多个存储单元，其中每个存储器单元可编程以存储数据具有第一逻辑值或第二逻辑值。数据扫描单元被配置为在存储器单元中要编程的多个数据之间搜索以识别具有第二逻辑值的数据。程序单元被配置为对具有第二逻辑值的识别数据进行分组，并且将同一组的识别数据的至少一部分同时编程到存储器单元中。

30. 发明申请

US20100226172A1 METHOD OF READING DATA AND METHOD OF INPUTTING AND OUTPUTTING DATA IN NON-VOLATILE MEMORY DEVICE 失效
标题翻译：读取数据的方法和在非易失性存储器件中输入和输出数据的方法
公开(公告)号：US20100226172A1
公开(公告)日：2010-09-09
申请号：US12712769
申请日：2010-02-25
申请人： In-Mo Kim , Jae-Yong Jeong
发明人： In-Mo Kim , Jae-Yong Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/34 , G11C11/5642 , G11C16/32
摘要： A method of reading data in a non-volatile memory device based on the logic level of a selection bit of an address, determines an order of reading a first and second bits of data stored in one multi-level memory cell corresponding to the address based on the logic level of the selection bit, and senses and outputs the first and second bits of data according to the determined order of reading. The method of reading data in a non-volatile memory device and the method of inputting and outputting data in a non-volatile memory device may reduce the initial read time by selecting the order of reading the first and second bits of data stored in the multi-level memory cell and reading the data according the order based on the start address.
摘要翻译：一种基于地址的选择位的逻辑电平读取非易失性存储器件中的数据的方法，确定读取与基于地址对应的一个多级存储器单元中存储的数据的第一和第二位的顺序在选择位的逻辑电平上，根据确定的读数顺序来感测和输出数据的第一和第二位。在非易失性存储器件中读取数据的方法以及在非易失性存储器件中输入和输出数据的方法可以通过选择读取多重存储器中存储的数据的第一和第二位的顺序来减少初始读取时间级存储单元，并根据开始地址按顺序读取数据。

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