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21. 发明申请

US20090256610A1 Quadrature phase correction circuit 有权
标题翻译：正交相位校正电路
公开(公告)号：US20090256610A1
公开(公告)日：2009-10-15
申请号：US12215829
申请日：2008-06-30
申请人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
发明人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
IPC分类号： H03K5/13
CPC分类号： H03L7/0814 , H03K2005/00286 , H03L7/087
摘要： A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out; a storage configured to store N-bit code values according to a plurality of detected phase differences; and a controller configured to share the N-bit code counter, control the generation of the N-bit code values according to the plurality of detected phase differences, and control the storing of the N-bit code values in an allocated space of the storage.
摘要翻译：正交相位校正电路包括N比特码计数器，被配置为当进行正交相位校正时根据检测到的相位差产生N比特码值; 存储器，被配置为根据多个检测到的相位差来存储N位代码值; 以及控制器，其被配置为共享所述N位代码计数器，根据所述多个检测到的相位差来控制所述N位代码值的生成，并且控制所述N位代码值在所述存储器的分配空间中的存储。

22. 发明申请

US20090175116A1 CLOCK SYNCHRONIZATION CIRCUIT AND OPERATION METHOD THEREOF 失效
标题翻译：时钟同步电路及其操作方法
公开(公告)号：US20090175116A1
公开(公告)日：2009-07-09
申请号：US12165045
申请日：2008-06-30
申请人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon , Dae-Kum Yoon
发明人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon , Dae-Kum Yoon
IPC分类号： G11C8/18 , H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , G11C8/18 , H03K2005/00208 , H03L7/0805 , H03L7/083 , H03L7/0891 , H03L7/0995 , H03L7/24
摘要： A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.
摘要翻译：一种具有时钟同步电路的半导体存储器件，其能够执行期望的相位/频率锁定操作，而没有抖动峰化现象和使用注入锁定的振荡控制电压信号的模式抖动。该装置包括锁相环，其检测反馈时钟信号和参考时钟信号之间的相位/频率差，以产生对应于检测到的相位/频率差的振荡控制电压信号，并产生对应于振荡控制电压信号。注入锁定振荡单元响应于振荡控制电压信号建立自由运行频率，并产生与参考时钟信号同步的内部时钟信号。

23. 发明申请

US20090168552A1 Semiconductor memory device and method for operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20090168552A1
公开(公告)日：2009-07-02
申请号：US12150912
申请日：2008-05-01
申请人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
发明人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
IPC分类号： G11C7/00 , G11C8/00 , H03K5/13 , H03L7/06
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1072 , G11C7/222 , H03L7/0814
摘要： A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.
摘要翻译：半导体存储器件包括边缘检测器，被配置为接收两对互补时钟以检测时钟的边沿;比较器，被配置为比较边缘检测器的输出信号，以检测同一对的时钟是否具有180度的相位差;以及检测不同对的时钟是否具有90度的相位差，控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器，被配置为校正时钟的相位响应于控制信号。

24. 发明授权

US08922251B2 Buffer control circuit and integrated circuit including the same 有权
标题翻译：缓冲器控制电路和集成电路包括相同
公开(公告)号：US08922251B2
公开(公告)日：2014-12-30
申请号：US13333983
申请日：2011-12-21
申请人： Taek-Sang Song , Dae-Han Kwon
发明人： Taek-Sang Song , Dae-Han Kwon
IPC分类号： H03B1/00 , H03K3/00 , H03K5/24 , H03K19/00 , H03K19/0948
CPC分类号： H03K5/2481 , H03K19/0027 , H03K19/0948
摘要： A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.
摘要翻译：缓冲器控制电路包括：电流供给单元，被配置为响应于代码提供电流并调节电流;放大缓冲器，被配置为使用电流进行操作并输出通过比较参考电位和参考电位获得的值;配置的第二缓冲器以缓冲第一缓冲器的输出;以及代码生成单元，被配置为响应于第二缓冲器的输出而生成代码。

25. 发明授权

US08004336B2 Semiconductor memory device and method for operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08004336B2
公开(公告)日：2011-08-23
申请号：US12150912
申请日：2008-05-01
申请人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
发明人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
IPC分类号： H03H11/16 , H03K5/13
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1072 , G11C7/222 , H03L7/0814
摘要： A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.
摘要翻译：半导体存储器件包括边缘检测器，被配置为接收两对互补时钟以检测时钟的边沿;比较器，被配置为比较边缘检测器的输出信号，以检测同一对的时钟是否具有180度的相位差;以及检测不同对的时钟是否具有90度的相位差，控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器，被配置为校正时钟的相位响应于控制信号。

26. 发明申请

US20100237922A1 CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD THEREOF 有权
标题翻译：时钟发生电路及其产生方法
公开(公告)号：US20100237922A1
公开(公告)日：2010-09-23
申请号：US12795132
申请日：2010-06-07
申请人： Dae-Han KWON , Taek-Sang Song
发明人： Dae-Han KWON , Taek-Sang Song
IPC分类号： H03H11/16
CPC分类号： G06F1/06
摘要： A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.
摘要翻译：一种时钟发生电路，包括：脉冲发生单元，用于基于参考时钟产生多个脉冲信号;每个脉冲信号具有相同的周期;相邻脉冲信号之间的相位差是第一相位差; 以及多相时钟发生单元，用于生成多个多相时钟，相邻的多相时钟之间的相位差等于脉冲信号对的脉冲信号之间的第二相位差，基于多个单位接收脉冲信号对的相位时钟发生单元。

27. 发明授权

US07760002B2 Clock generating circuit and clock generating method thereof 有权
标题翻译：时钟发生电路及其时钟产生方法
公开(公告)号：US07760002B2
公开(公告)日：2010-07-20
申请号：US12325346
申请日：2008-12-01
申请人： Dae-Han Kwon , Taek-Sang Song
发明人： Dae-Han Kwon , Taek-Sang Song
IPC分类号： G06F1/06
CPC分类号： G06F1/06
摘要： A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs.
摘要翻译：一种时钟发生电路，包括：脉冲发生单元，用于基于参考时钟产生多个脉冲信号;每个脉冲信号具有相同的周期;相邻脉冲信号之间的相位差是第一相位差; 以及多相时钟发生单元，用于生成多个多相时钟，相邻的多相时钟之间的相位差等于脉冲信号对的脉冲信号之间的第二相位差，基于多个单位接收脉冲信号对的相位时钟发生单元。

28. 发明申请

US20090302891A1 OUTPUT DRIVER 有权
标题翻译：输出驱动器
公开(公告)号：US20090302891A1
公开(公告)日：2009-12-10
申请号：US12326990
申请日：2008-12-03
申请人： Kyung-Hoon Kim , Dae-Han Kwon , Taek-Sang Song
发明人： Kyung-Hoon Kim , Dae-Han Kwon , Taek-Sang Song
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528
摘要： There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal.
摘要翻译：提供了一种输出驱动器，其包括配置为响应于数据信号产生主驱动控制信号的预驱动器，配置成响应于主驱动控制信号驱动输出端的主驱动器，辅助驱动控制信号发生器，其被配置为产生具有与数据信号和间隔控制信号对应的激活间隔的辅助驱动控制信号，以及配置为响应于辅助驱动控制信号来驱动输出端子的辅助驱动器。

29. 发明申请

US20090168944A1 LOW PASS FILTER AND LOCK DETECTOR CIRCUIT 有权
标题翻译：低通滤波器和锁定检测电路
公开(公告)号：US20090168944A1
公开(公告)日：2009-07-02
申请号：US12344552
申请日：2008-12-28
申请人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon , Dae-Kun Yoon
发明人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon , Dae-Kun Yoon
IPC分类号： H03D3/24
CPC分类号： H03L7/095 , G01R29/0273 , H03K5/153 , H03K2005/00065 , H03K2005/00071 , Y10S331/02
摘要： A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.
摘要翻译：低通滤波器包括被配置为输出与输入脉冲宽度成比例的电压的驱动器单元，被配置为对驱动器单元的输出电压进行充电的充电/放电单元，被配置为比较充电/放电的输出电压具有参考值的单元以输出方波信号;以及切换单元，被配置为基于带宽扩展信号将充电/放电单元切换到操作状态。

30. 发明申请

US20090128208A1 APPARATUS AND METHOD FOR DETECTING DUTY RATIO OF SIGNALS IN SEMICONDUCTOR DEVICE CIRCUIT 审中-公开
标题翻译：用于检测半导体器件电路中信号占空比的装置和方法
公开(公告)号：US20090128208A1
公开(公告)日：2009-05-21
申请号：US12263690
申请日：2008-11-03
申请人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon , Dae-Kun Yoon
发明人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon , Dae-Kun Yoon
IPC分类号： H03K3/017
CPC分类号： H03K3/017
摘要： Apparatus for detecting duty ratio of signals in semiconductor device circuit includes a circuit for detecting a duty ratio of signals in a semiconductor device includes a comparing unit which compares a duty cycle of first and second input clock signals input differentially and generates a first output signal and a second output signal, a latching unit which stores the first and second output signals and generates a detected signal corresponding to the first and second output signals, and an adjusting unit which receives the first and the second output signals, and transmits the first and the second output signals to the latching unit based on a voltage level difference of the first and second output signals.
摘要翻译：用于检测半导体器件电路中的信号占空比的装置包括用于检测半导体器件中的信号的占空比的电路，包括比较单元，其比较差分输入的第一和第二输入时钟信号的占空比并产生第一输出信号，第二输出信号，存储第一和第二输出信号并产生对应于第一和第二输出信号的检测信号的锁存单元，以及接收第一和第二输出信号的调整单元，并且发送第一和第二输出信号基于第一和第二输出信号的电压电平差，向锁存单元输出第二输出信号。

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