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21. 发明授权

US07467260B2 Method and apparatus to purge remote node cache lines to support hot node replace in a computing system 有权
标题翻译：清除远程节点缓存行以支持计算系统中的热节点替换的方法和装置
公开(公告)号：US07467260B2
公开(公告)日：2008-12-16
申请号：US10961746
申请日：2004-10-08
申请人： Duane Arlyn Averill , John Michael Borkenhagen , Philip Rogers Hillier, III
发明人： Duane Arlyn Averill , John Michael Borkenhagen , Philip Rogers Hillier, III
IPC分类号： G06F12/00
CPC分类号： G06F12/0808 , G06F12/0804 , G06F12/126
摘要： An apparatus and method is disclosed for flushing a cache in a computing system. In a multinode computing system a cache in a first node may contain modified data in an address space of a second node. The cache in the first node must be purged prior to shutting down the first node. The computing system uses a random class replacement scheme for the cache. A cache flush routine sets a cache flush mode in a class replace select mechanism, overriding the random class replacement scheme. With the random class replacement scheme overridden, a minimum number of fetches will flush all the cache lines in the cache, each fetch loading the cache with a cache line not already in the cache. No additional delay penalty is incurred in a critical path through which fetches and stores to the cache must pass.
摘要翻译：公开了一种用于在计算系统中刷新高速缓存的装置和方法。在多节点计算系统中，第一节点中的高速缓存可以包含第二节点的地址空间中的修改数据。必须在关闭第一个节点之前清除第一个节点中的缓存。计算系统对缓存使用随机类替换方案。缓存刷新例程在类替换选择机制中设置缓存刷新模式，覆盖随机类替换方案。随着随机类替换方案被覆盖，最小数量的提取将刷新缓存中的所有高速缓存行，每次使用尚未在高速缓存中的缓存行来提取缓存。在缓存提取和存储必须通过的关键路径中不会产生额外的延迟损失。

22. 发明申请

US20080201495A1 HANDLING DMA OPERATIONS DURING A PAGE COPY 有权
标题翻译：在页面复制中处理DMA操作
公开(公告)号：US20080201495A1
公开(公告)日：2008-08-21
申请号：US12112932
申请日：2008-04-30
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.
摘要翻译：存储器控制器提供页面复制逻辑，以便在由存储器控制器复制页面期间在页面的DMA操作发生时确保数据一致性。页面复制逻辑将DMA操作的页面索引与指示当前正在复制的位置的复制地址指针进行比较。如果DMA操作的页面索引小于复制地址指针，则DMA操作将被写入的页面部分已被复制，因此DMA操作被执行到新页面的物理地址。如果DMA操作的页面索引大于复制地址指针，则DMA操作将被写入的页面部分尚未被复制，因此DMA操作被执行到旧页面的物理地址。

23. 发明授权

US07392445B2 Autonomic bus reconfiguration for fault conditions 失效
标题翻译：自动总线重新配置故障条件
公开(公告)号：US07392445B2
公开(公告)日：2008-06-24
申请号：US10660217
申请日：2003-09-11
申请人： John Michael Borkenhagen , Laura Marie Zumbrunnen
发明人： John Michael Borkenhagen , Laura Marie Zumbrunnen
IPC分类号： G01R31/28
CPC分类号： G06F11/2005
摘要： Methods and apparatus are provided that allow an electronic system having a signaling bus with a fault on a signaling conductor to operate at a degraded performance. A block of data is transferred from a first electronic unit to a second electronic unit over the signaling bus. A transmission sequence sends the block of data using all of the nonfaulty signaling conductors using a minimum number of beats required to complete the transmission.
摘要翻译：提供了允许具有在信令导体上具有故障的信令总线的电子系统以降级的性能来操作的方法和装置。数据块通过信令总线从第一电子单元传送到第二电子单元。传输序列使用所有非故障信令导体使用完成传输所需的最小次数发送数据块。

24. 发明申请

US20080028126A1 Memory System Having an Apportionable Data Bus and Daisy Chained Memory Chips 有权
标题翻译：具有可分配数据总线和菊花链内存芯片的内存系统
公开(公告)号：US20080028126A1
公开(公告)日：2008-01-31
申请号：US11459959
申请日：2006-07-26
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
IPC分类号： G06F12/00 , G06F13/40
CPC分类号： G06F13/1684
摘要： A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a data bus chain having a number of data bus bits. The data bus chain has a first portion of data bus bits dedicated to transmitting write data from the memory controller to a memory chip. The data bus chain has a second portion of data bus bits dedicated to transmitting read data from a memory chip to the memory controller. Apportionment of data bus bits between the first portion and the second portion is programmable. Programming is done by pin connection, scanning of a value, or by request from a processor coupled to the memory controller.
摘要翻译：一种具有存储器控制器和存储器芯片的菊花链的存储器系统。存储器控制器通过地址/命令总线链耦合到存储器芯片的菊花链中的存储器芯片。存储器控制器通过具有多个数据总线位的数据总线链耦合到存储器芯片的菊花链中的存储器芯片。数据总线链具有专用于从存储器控制器向存储器芯片发送写数据的数据总线位的第一部分。数据总线链具有专用于从存储器芯片向存储器控制器发送读取数据的数据总线位的第二部分。数据总线位在第一部分和第二部分之间的分配是可编程的。编程通过引脚连接，值的扫描，或者通过与存储器控制器耦合的处理器的请求来完成。

25. 发明授权

US07309911B2 Method and stacked memory structure for implementing enhanced cooling of memory devices 有权
标题翻译：用于实现存储器件的增强冷却的方法和堆叠存储器结构
公开(公告)号：US07309911B2
公开(公告)日：2007-12-18
申请号：US11138939
申请日：2005-05-26
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Hugh Cochran , William Paul Hovis , Paul Rudrud
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Hugh Cochran , William Paul Hovis , Paul Rudrud
IPC分类号： H01L23/495
CPC分类号： H01L25/105 , H01L25/18 , H01L2225/107 , H01L2225/1094 , H01L2924/0002 , H01L2924/1627 , H01L2924/00
摘要： A method and structure are provided for implementing enhanced cooling of a plurality of memory devices. The memory structure includes a stack of platters. A sub-plurality of memory devices is mounted on each platter. At least one connector is provided with each platter for connecting to the sub-plurality of memory devices. A heat sink is associated with the stack of platters for cooling the plurality of memory devices.
摘要翻译：提供了一种用于实现多个存储器件的增强冷却的方法和结构。存储器结构包括堆叠的盘片。每个盘片上安装有多个存储器件。至少一个连接器设置有每个盘片，用于连接到子多个存储器件。散热器与用于冷却多个存储器件的盘堆相关联。

26. 发明授权

US5790843A System for modifying microprocessor operations independently of the execution unit upon detection of preselected opcodes 失效
标题翻译：用于在检测到预先选定的操作码时，独立于执行单元修改微处理器操作的系统
公开(公告)号：US5790843A
公开(公告)日：1998-08-04
申请号：US718180
申请日：1996-09-19
申请人： John Michael Borkenhagen , William Thomas Flynn , Philip Rodgers Hillier, III , Andrew Henry Wottreng
发明人： John Michael Borkenhagen , William Thomas Flynn , Philip Rodgers Hillier, III , Andrew Henry Wottreng
IPC分类号： G06F9/318 , G06F9/445 , G06F9/00
CPC分类号： G06F9/3017 , G06F8/66 , G06F9/328
摘要： Described herein is a system and method for providing instruction dependent execution control on a microprocessor device. The system and method utilize instruction match register/execution control register (IMR/ECR) pairs to first identify known problematic instructions and to then alter control of the microprocessor in a preselected manner when processing each problematic instruction. The invention contemplates the use of numerous control options for altering control of the microprocessor.
摘要翻译：这里描述了一种用于在微处理器设备上提供依赖于指令的执行控制的系统和方法。系统和方法利用指令匹配寄存器/执行控制寄存器（IMR / ECR）对来首先识别已知的有问题的指令，然后在处理每个有问题的指令时以预先选择的方式改变微处理器的控制。本发明考虑使用许多控制选项来改变微处理器的控制。

27. 发明授权

US07921271B2 Hub for supporting high capacity memory subsystem 有权
标题翻译：用于支持高容量内存子系统的集线器
公开(公告)号：US07921271B2
公开(公告)日：2011-04-05
申请号：US11769019
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F13/18
CPC分类号： G06F13/4243
摘要： A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.
摘要翻译：高容量存储器子系统架构利用布置在一个或多个簇中的多个存储器模块，每个存储器模块连接到相应的集线器，该集线器又连接到存储器控制器。在集群内，数据被交织，以便每个数据访问命令访问集群的所有模块。集线器以较低的总线频率与存储器模块通信，但是在多个模块之间分配数据使集群能够保持存储器 - 控制器到集线器总线的复合数据速率。优选地，存储器系统采用具有双模操作的缓冲存储器芯片，其中之一支持数据被交错的集群配置，并且通信总线以减小的总线宽度和/或减少的总线频率进行操作以匹配交织级别。

28. 发明授权

US07783793B2 Handling DMA operations during a page copy 有权
标题翻译：在页面复制期间处理DMA操作
公开(公告)号：US07783793B2
公开(公告)日：2010-08-24
申请号：US12112932
申请日：2008-04-30
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
IPC分类号： G06F13/28 , G06F12/00 , G06F13/00
CPC分类号： G06F13/28
摘要： A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.
摘要翻译：存储器控制器提供页面复制逻辑，以便在由存储器控制器复制页面期间在页面的DMA操作发生时确保数据一致性。页面复制逻辑将DMA操作的页面索引与指示当前正在复制的位置的复制地址指针进行比较。如果DMA操作的页面索引小于复制地址指针，则DMA操作将被写入的页面部分已被复制，因此DMA操作被执行到新页面的物理地址。如果DMA操作的页面索引大于复制地址指针，则DMA操作将被写入的页面部分尚未被复制，因此DMA操作被执行到旧页面的物理地址。

29. 发明授权

US07725620B2 Handling DMA requests in a virtual memory environment 有权
标题翻译：在虚拟内存环境中处理DMA请求
公开(公告)号：US07725620B2
公开(公告)日：2010-05-25
申请号：US11246824
申请日：2005-10-07
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
IPC分类号： G06F13/28 , G06F3/00 , G06F5/00 , G06F13/00 , G06F9/34
CPC分类号： G06F13/28
摘要： An apparatus includes a virtual memory manager that moves data from a first block to second block in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block.
摘要翻译：一种装置包括将数据从第一块移动到存储器中的第二块的虚拟存储器管理器。当虚拟存储器管理器准备好将数据从第一块传送到第二块时，定义第三个临时存储块。将DMA控制器中的转换表更改为将目标为第一个块的DMA传输指向临时块。然后，虚拟存储器管理器将数据从第一块传送到第二块。当传输完成时，检查DMA是否将数据传输到临时块，而第一个块的数据正在写入第二个块。如果是这样，则将写入临时块的数据写入第二块。优选地使用硬件寄存器来有效地检测对临时块的改变。

30. 发明授权

US07675949B2 Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces 有权
标题翻译：动态重构固态存储器件，通过多个数据接口复制和定时复用数据
公开(公告)号：US07675949B2
公开(公告)日：2010-03-09
申请号：US12273883
申请日：2008-11-19
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Paul Rudrud
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Paul Rudrud
IPC分类号： H04J3/02
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C7/1093 , G11C7/1096 , G11C29/022 , G11C2029/0409
摘要： Multiple interfaces dedicated to individual logic circuits such as memory arrays are capable of being dynamically reconfigured from operating separately and in parallel to operating in a more collective manner to ensure that data associated with all of the logic circuits will be communicated irrespective of a failure in any of the interfaces. Specifically, a plurality of interfaces, each of which being ordinarily configured to communicate data associated with an associated logic circuit in parallel with the other interfaces, may be dynamically reconfigured, e.g., in response to a detected failure in one or more of the interfaces, to communicate data associated with each of the interfaces over each of at least a subset of the interfaces in a time multiplexed and replicated manner.
摘要翻译：专用于各个逻辑电路（例如存储器阵列）的多个接口能够被动态地重新配置，以独立运行并行并行地以更集体的方式运行，以确保与所有逻辑电路相关联的数据将被传送，而不管任何的接口。具体地，可以动态地重新配置多个接口，每个接口通常被配置为与其他接口并行地传送与相关联的逻辑电路相关联的数据，例如响应于一个或多个接口中检测到的故障，以时间复用和复制的方式在接口的至少一个子集中的每一个上传送与每个接口相关联的数据。

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