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21. 发明申请

US20050179073A1 Integrated circuit devices having buried insulation layers and methods of forming the same 失效
标题翻译：具有掩埋绝缘层的集成电路器件及其形成方法
公开(公告)号：US20050179073A1
公开(公告)日：2005-08-18
申请号：US10722193
申请日：2003-11-26
申请人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
发明人： Byeong-chan Lee , Si-young Choi , Jong-ryeol Yoo , Yong-hoon Son , In-soo Jung , Deok-hyung Lee
IPC分类号： H01L21/8234 , H01L21/8242 , H01L29/76
CPC分类号： H01L27/10873 , H01L21/823425 , H01L21/823481 , H01L27/10888
摘要： An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.
摘要翻译：集成电路器件包括形成在集成电路器件的有源区上的栅电极和与有源区相邻的场隔离层。源极区域和漏极区域在栅电极的交替侧上的有源区域中。至少一个掩埋绝缘层位于漏极区域或源极区域之下。

22. 发明授权

US06890823B2 Methods of forming integrated circuits with thermal oxide layers on side walls of gate electrodes wherein the source and drain are higher than the gate electrode 有权
标题翻译：在栅电极的侧壁上形成具有热氧化层的集成电路的方法，其中源极和漏极高于栅电极
公开(公告)号：US06890823B2
公开(公告)日：2005-05-10
申请号：US10426562
申请日：2003-04-30
申请人： Byeong-chan Lee , Si-young Choi , Chul-sung Kim , Jong-ryeol Yoo , Deok-hyung Lee
发明人： Byeong-chan Lee , Si-young Choi , Chul-sung Kim , Jong-ryeol Yoo , Deok-hyung Lee
IPC分类号： H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/76889 , H01L21/823425 , H01L21/823443 , H01L21/823468 , H01L29/6656
摘要： Methods of forming thermal oxide layers on a side wall of gate electrodes are disclosed. In particular, thermal oxide layers can be formed on a side wall of a gate electrode by forming a gate electrode on an integrated circuit substrate and forming a thermal oxide layer on a side wall of the gate electrode using a thermal oxidation process. A silicide layer can be formed on the gate electrode after the formation of the thermal oxide layer.
摘要翻译：公开了在栅电极的侧壁上形成热氧化层的方法。特别地，可以通过在集成电路基板上形成栅电极并使用热氧化工艺在栅电极的侧壁上形成热氧化层，在栅电极的侧壁上形成热氧化物层。在形成热氧化物层之后，可以在栅电极上形成硅化物层。

23. 发明授权

US08871104B2 Method of forming pattern, reticle, and computer readable medium for storing program for forming pattern 有权
标题翻译：形成图案，掩模版和用于存储用于形成图案的程序的计算机可读介质的方法
公开(公告)号：US08871104B2
公开(公告)日：2014-10-28
申请号：US13221606
申请日：2011-08-30
申请人： Dong-woon Park , Hyun-jong Lee , Si-young Choi , Yong-kug Bae
发明人： Dong-woon Park , Hyun-jong Lee , Si-young Choi , Yong-kug Bae
IPC分类号： G06F17/50 , H01L21/027 , H01L21/033 , G03F1/70
CPC分类号： H01L21/0337 , G03F1/70 , G06F17/5081 , Y10S438/947
摘要： A method of forming a pattern includes forming a plurality of target patterns, forming a plurality of pitch violating patterns that make contact with the plurality of target patterns and are disposed between the plurality of target patterns, classifying the plurality of pitch violating patterns into a first region and a second region adjacent to the first region, and forming an initial pattern corresponding to one of the first region and the second region.
摘要翻译：形成图案的方法包括：形成多个目标图案，形成与多个目标图案接触并设置在多个目标图案之间的多个倾斜违规图案，将多个倾斜违规图案分类为第一区域和与第一区域相邻的第二区域，并且形成对应于第一区域和第二区域之一的初始图案。

24. 发明授权

US08373165B2 Semiconductor integrated circuit device and a method of fabricating the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08373165B2
公开(公告)日：2013-02-12
申请号：US13343967
申请日：2012-01-05
申请人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/04
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

25. 发明授权

US08330207B2 Flash memory device including multilayer tunnel insulator and method of fabricating the same 失效
标题翻译：包括多层隧道绝缘体的闪存器件及其制造方法
公开(公告)号：US08330207B2
公开(公告)日：2012-12-11
申请号：US12003992
申请日：2008-01-04
申请人： Sung-kweon Baek , Sang-ryol Yang , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Jin-tae Noh
发明人： Sung-kweon Baek , Sang-ryol Yang , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Jin-tae Noh
IPC分类号： H01L29/788 , H01L21/04
CPC分类号： H01L29/513 , H01L21/28273 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.
摘要翻译：一种闪存装置，包括在基板上的下部隧道绝缘层，下部隧道绝缘层上的上部隧道绝缘层和上部隧道绝缘层上的P型栅极，其中上部隧道绝缘层包括无定形氧化物层。

26. 发明授权

US07888246B2 Semiconductor integrated circuit device and a method of fabricating the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07888246B2
公开(公告)日：2011-02-15
申请号：US12073315
申请日：2008-03-04
申请人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
发明人： Yong-hoon Son , Si-young Choi , Jong-wook Lee
IPC分类号： H01L21/36
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

27. 发明申请

US20100117141A1 Memory cell transistors having limited charge spreading, non-volatile memory devices including such transistors, and methods of formation thereof 审中-公开
标题翻译：具有有限电荷扩展的存储单元晶体管，包括这种晶体管的非易失性存储器件及其形成方法
公开(公告)号：US20100117141A1
公开(公告)日：2010-05-13
申请号：US12590641
申请日：2009-11-12
申请人： Dong-woon Shin , Young-Kun Park , Jun-gyu Yang , Jae-young Ahn , Ki-hyun Hwang , Si-young Choi
发明人： Dong-woon Shin , Young-Kun Park , Jun-gyu Yang , Jae-young Ahn , Ki-hyun Hwang , Si-young Choi
IPC分类号： H01L27/105 , H01L29/792
CPC分类号： H01L27/11582 , G11C5/02 , G11C16/0475 , G11C16/0483 , H01L27/11568 , H01L27/11578 , H01L29/40117 , H01L29/4234 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In one aspect, a transistor comprises: a substrate body; a tunnel oxide layer on the body; a charge trapping layer on the tunnel oxide layer; a blocking layer on the charge trapping layer; a control gate on the blocking layer, the control gate having first and second sidewalls, the first and second sidewalls being spaced apart from each other by a first distance; and charge confinement features on the body, the charge confinement features being spaced apart from each other by a second distance that is greater than or substantially equal to the first distance, the charge confinement features suppressing or preventing migration of charge present in the charge trapping layer.
摘要翻译：一方面，晶体管包括：衬底本体; 身体上的隧道氧化层; 隧道氧化层上的电荷捕获层; 电荷俘获层上的阻挡层; 所述阻挡层上的控制栅极，所述控制栅极具有第一和第二侧壁，所述第一和第二侧壁彼此隔开第一距离; 并且在身体上充电限制特征，所述电荷限制特征彼此间隔开大于或基本上等于所述第一距离的第二距离，所述电荷限制特征抑制或防止存在于所述电荷俘获层中的电荷的迁移。

28. 发明申请

US20090179252A1 Flash memory device including multilayer tunnel insulator and method of fabricating the same 审中-公开
标题翻译：包括多层隧道绝缘体的闪存器件及其制造方法
公开(公告)号：US20090179252A1
公开(公告)日：2009-07-16
申请号：US12292674
申请日：2008-11-24
申请人： Sung-kweon Baek , Sang-ryol Yang , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Dong-kak Lee
发明人： Sung-kweon Baek , Sang-ryol Yang , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Dong-kak Lee
IPC分类号： H01L29/788 , H01L29/423 , H01L29/68
CPC分类号： H01L29/7883 , H01L29/40114 , H01L29/42324 , H01L29/513
摘要： A flash memory device may include a lower tunnel insulation layer disposed on a substrate, an upper tunnel insulation layer disposed on the lower tunnel insulation layer, a floating gate disposed on the upper tunnel insulation layer, an intergate insulation layer disposed on the floating gate; and a control gate disposed on the intergate insulation layer.
摘要翻译：闪存器件可以包括设置在衬底上的下部隧道绝缘层，设置在下部隧道绝缘层上的上部隧道绝缘层，设置在上部隧道绝缘层上的浮动栅极，设置在浮动栅极上的栅极间绝缘层; 以及设置在隔间绝缘层上的控制栅极。

29. 发明申请

US20080305620A1 METHODS OF FORMING DEVICES INCLUDING DIFFERENT GATE INSULATING LAYERS ON PMOS/NMOS REGIONS 有权
标题翻译：在PMOS / NMOS区域形成不同栅绝缘层的器件的方法
公开(公告)号：US20080305620A1
公开(公告)日：2008-12-11
申请号：US12130646
申请日：2008-05-30
申请人： Sang-jin Hyun , Si-young Choi , In-sang Jeom , Gab-jin Nam , Sang-bom Kang , Sug-hun Hong
发明人： Sang-jin Hyun , Si-young Choi , In-sang Jeom , Gab-jin Nam , Sang-bom Kang , Sug-hun Hong
IPC分类号： H01L21/425
CPC分类号： H01L21/823857 , H01L21/28202 , H01L21/31155 , H01L29/513 , H01L29/518
摘要： Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.
摘要翻译：提供一种制造半导体器件的方法，其中可以控制CMOS器件的栅极绝缘层的厚度。该方法可以包括将氟（F）选择性地注入到衬底上的第一区域中，并且避免将氟（F）注入到衬底上的第二区域中。第一栅极绝缘层由第一和第二区域上的氧氮化物层形成，以分别具有第一和第二厚度，其中第一厚度小于第二厚度。在第一栅极绝缘层上形成第二栅极绝缘层，并且在第二栅极绝缘层上形成栅电极图案。

30. 发明申请

US20080116530A1 Semiconductor Devices Having Transistors with Different Gate Structures and Related Methods 审中-公开
标题翻译：具有不同栅极结构的晶体管的半导体器件及相关方法
公开(公告)号：US20080116530A1
公开(公告)日：2008-05-22
申请号：US11855413
申请日：2007-09-14
申请人： Sang-jin Hyun , Si-young Choi , In-sang Jeon , Sang-bom Kang , Hye-min Kim
发明人： Sang-jin Hyun , Si-young Choi , In-sang Jeon , Sang-bom Kang , Hye-min Kim
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823828 , H01L21/823437 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10876 , H01L27/10894 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66621
摘要： A semiconductor device may include a semiconductor substrate and first and second transistors. The first transistor may have a first gate structure on the semiconductor substrate, and the first gate structure may include a first gate insulating layer between a first gate electrode and the semiconductor substrate. The first gate insulating layer may include first and second dielectric materials with the second dielectric material having a greater dielectric constant than the first dielectric material. Moreover, the first gate electrode may be in contact with the second dielectric material. The second transistor may have a second gate structure on the semiconductor substrate, with the second gate structure including a second gate insulating layer between a second gate electrode and the semiconductor substrate. Related methods are also discussed.
摘要翻译：半导体器件可以包括半导体衬底和第一和第二晶体管。第一晶体管可以在半导体衬底上具有第一栅极结构，并且第一栅极结构可以包括在第一栅极电极和半导体衬底之间的第一栅极绝缘层。第一栅极绝缘层可以包括第一和第二介电材料，其中第二介电材料具有比第一介电材料更大的介电常数。此外，第一栅电极可以与第二电介质材料接触。第二晶体管可以在半导体衬底上具有第二栅极结构，其中第二栅极结构包括在第二栅电极和半导体衬底之间的第二栅极绝缘层。还讨论了相关方法。

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