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    • 30. 发明申请
    • Hardware and Software Co-test Method for FPGA
    • FPGA的硬件和软件协同测试方法
    • US20090100304A1
    • 2009-04-16
    • US12238674
    • 2008-09-26
    • Ping LiYongbo LiaoAiwu RuanWei LiWenchang Li
    • Ping LiYongbo LiaoAiwu RuanWei LiWenchang Li
    • G01R31/3177G06F11/25
    • G01R31/318516
    • A hardware and software co-test method for FPGA comprises the following steps of: setting up a HW/SW co-test system comprising a PC, a software part, HW/SW communication modules, a hardware accelerator for testing a DUT FPGA which is mapped with a configuration file of DUT; predefining a table of test vectors for FPGA by software part in PC; generating configuration files based on the tables of test vector for I/O module, CLB and routing matrix, and then sending the configuration file into DUT FPGA to configure the FPGA; testing DUT FPGA in terms of the tables of test vector for lo I/O module, CLB and routing matrix, and returning results to the software part; and comparing the test results with expected data in the software part, generating a test report, and during the above steps, the error cells in the FPGA are capable of being automatically positioned.
    • FPGA的硬件和软件协同测试方法包括以下步骤:建立包括PC,软件部分,HW / SW通信模块,用于测试DUT FPGA的硬件加速器的HW / SW协同测试系统, 用DUT的配置文件映射; 通过PC中的软件部分预先定义FPGA测试向量表; 根据I / O模块,CLB和路由矩阵的测试向量表生成配置文件,然后将配置文件发送到DUT FPGA配置FPGA; 根据Lo I / O模块,CLB和路由矩阵的测试向量表,测试DUT FPGA,并将结果返回到软件部分; 并将测试结果与软件部分中的预期数据进行比较,生成测试报告,并且在上述步骤中,FPGA中的错误单元能够自动定位。