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21. 发明授权

US5703521A Circuit configuration for monitoring the temperature of a power semiconductor component 失效
标题翻译：用于监测功率半导体元件的温度的电路配置
公开(公告)号：US5703521A
公开(公告)日：1997-12-30
申请号：US625634
申请日：1996-03-29
申请人： Josef-Matthias Gantioler , Holger Heil , Jenoe Tihanyi
发明人： Josef-Matthias Gantioler , Holger Heil , Jenoe Tihanyi
IPC分类号： G01K7/01 , H01L21/822 , H01L27/04 , H01L35/00 , H03K5/153
CPC分类号： G01K7/01
摘要： The temperature of a power semiconductor component is monitored by feeding the block current of a bipolar transistor which is in thermal contact with the component to an amplifying current mirror. The output signal of the current mirror is compared with a reference current. If the mirrored current is greater than the reference current, then the system produces a corresponding output. Temperatures of the power semiconductor component below 140.degree. C. can be reliably detected.
摘要翻译：通过将与元件热接触的双极晶体管的块电流馈送到放大电流镜来监测功率半导体元件的温度。将电流镜的输出信号与参考电流进行比较。如果镜像电流大于参考电流，则系统产生相应的输出。可以可靠地检测低于140℃的功率半导体组件的温度。

22. 发明授权

US5672893A Protective configuration against electrostatic discharges in semiconductor components controllable by field effect 失效
标题翻译：通过场效应控制的半导体元件中的静电放电的保护配置
公开(公告)号：US5672893A
公开(公告)日：1997-09-30
申请号：US590931
申请日：1996-01-24
申请人： Jenoe Tihanyi
发明人： Jenoe Tihanyi
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06 , H01L29/78 , H01L23/62 , H01L27/07
CPC分类号： H01L27/0259 , H01L2924/0002
摘要： A configuration for protecting a first semiconductor component being controllable by field effect against electrostatic discharges, includes a voltage-limiting, protective, second semiconductor component being connected to the gate terminal of the first semiconductor component. The second semiconductor component is an integrated bipolar transistor having a collector-to-emitter path being connected between the drain terminal and the gate terminal of the first semiconductor component.
摘要翻译：用于保护由静电放电效应控制的第一半导体部件的结构包括连接到第一半导体部件的栅极端子的限压保护的第二半导体部件。第二半导体部件是集成极 - 发射极路径连接在第一半导体部件的漏极端子和栅极端子之间的集成双极型晶体管。

23. 发明授权

US5434521A Integrated comparator circuit 失效
标题翻译：集成比较电路
公开(公告)号：US5434521A
公开(公告)日：1995-07-18
申请号：US978637
申请日：1992-11-19
申请人： Ludwig Leipold , Rainald Sander , Jenoe Tihanyi
发明人： Ludwig Leipold , Rainald Sander , Jenoe Tihanyi
IPC分类号： G01R19/165 , H03K5/08 , H03K17/30 , H03K17/687 , H03K5/153
CPC分类号： H03K17/6872 , G01R19/16519 , H03K17/302
摘要： An integrated comparator circuit includes two complementary MOSFETs having main current paths being connected together in a series circuit at a connecting point. An inverter stage has two complementary MOSFETs with gate terminals connected to the connecting point. First, second and third terminals are provided. The first and second terminals are for an operating voltage, and the second and third terminals are for a voltage to be compared. The series circuit is connected between the first and third terminals, and the inverter stage is connected between the first and second terminals. One of the MOSFETs of the series circuit connected to the first terminal and one of the MOSFETs of the inverter stage connected to the first terminal are of the same channel type. The other of the MOSFETs of the series circuit connected to the third terminal and the other of the MOSFETs of the inverter stage connected the second terminal are of the same channel type.
摘要翻译：集成比较器电路包括两个互补MOSFET，其中主电流路径在连接点处串联在一起连接在一起。反相器级具有两个互补MOSFET，栅极端子连接到连接点。首先，提供第二和第三终端。第一和第二端子用于工作电压，第二和第三端子用于比较电压。串联电路连接在第一和第三端子之间，变频器级连接在第一和第二端子之间。连接到第一端子的串联电路的MOSFET之一和连接到第一端子的反相器级的MOSFET之一具有相同的通道类型。连接到第三端子的串联电路的另一个MOSFET和连接到第二端子的反相器级的另一个MOSFET具有相同的通道类型。

24. 发明授权

US5371418A Drive circuit for a power MOSFET with load at the source side 失效
标题翻译：用于源极负载的功率MOSFET的驱动电路
公开(公告)号：US5371418A
公开(公告)日：1994-12-06
申请号：US95197
申请日：1993-07-23
申请人： Ludwig Leipold , Rainald Sander , Jenoe Tihanyi
发明人： Ludwig Leipold , Rainald Sander , Jenoe Tihanyi
IPC分类号： H01L27/088 , H03K17/00 , H03K17/06 , H03K17/687
CPC分类号： H03K17/6877 , H01L27/0883 , H03K17/063 , H03K2217/0036
摘要： Power FETs having a load at the source side require a gate voltage lying above the drain voltage in order to be driven completely conductive. This can occur with a known pump circuit. In the drive circuit disclosed, the diode connected to the gate terminal of the power FET is a depletion FET whose substrate terminal is applied to the oscillating voltage that is required for the operation of the pump circuit. The cut off voltage is thus synchronously set relative to the oscillating voltage such that low losses arise when loading C.sub.GS and an adequately high inhibit voltage can be built up when loading the pump capacitor.
摘要翻译：在源极处具有负载的功率FET需要位于漏极电压之上的栅极电压，以便被驱动完全导电。这可以用已知的泵电路进行。在所公开的驱动电路中，连接到功率FET的栅极端子的二极管是耗尽FET，其基极端子被施加到泵电路的操作所需的振荡电压。因此，截止电压相对于振荡电压被同步设定，使得当加载CGS时产生低损耗，并且当加载泵电容器时可以建立足够高的抑制电压。

25. 发明授权

US5272399A Circuit limiting the load current of a power MOSFET 失效
标题翻译：电路限制功率MOSFET的负载电流
公开(公告)号：US5272399A
公开(公告)日：1993-12-21
申请号：US4970
申请日：1993-01-15
申请人： Jenoe Tihanyi , Ludwig Leipold , Rainald Sander
发明人： Jenoe Tihanyi , Ludwig Leipold , Rainald Sander
IPC分类号： H02H7/20 , H03K17/08 , H03K17/082 , H03K3/01 , H03K5/08
CPC分类号： H03K17/0822
摘要： A circuit configuration for limiting current flowing through a power MOSFET includes a voltage divider being connected between drain and source terminals of the power MOSFET and having a node at which a voltage following a drain-to-source voltage of the power MOSFET drops. A control transistor has a load path connected between the gate terminal and the source terminal of the power MOSFET. The control transistor is made conducting as a function of the voltage at the node of the voltage divider if the drain-to-source voltage of the power MOSFET exceeds a predetermined value. A resistor is connected between the gate terminal of the control transistor and the gate terminal of the power MOSFET. A depletion FET has a drain terminal connected to the gate terminal of the control transistor. The source terminal of the depletion FET is connected to the node of the voltage divider. The gate terminal of the depletion FET is connected to the source terminal of the power MOSFET.
摘要翻译：用于限制流过功率MOSFET的电流的电路配置包括分压器，其连接在功率MOSFET的漏极和源极端子之间，并且具有在功率MOSFET的漏极 - 源极电压之后的电压下降的节点。控制晶体管具有连接在功率MOSFET的栅极端子和源极端子之间的负载路径。如果功率MOSFET的漏极 - 源极电压超过预定值，则控制晶体管作为分压器节点处的电压的函数导通。电阻连接在控制晶体管的栅极端子和功率MOSFET的栅极端子之间。耗尽FET具有连接到控制晶体管的栅极端子的漏极端子。耗尽FET的源极端子连接到分压器的节点。耗尽FET的栅极端子连接到功率MOSFET的源极端子。

26. 发明授权

US4951110A Power semiconductor structural element with four layers 失效
标题翻译：功率半导体结构元件四层
公开(公告)号：US4951110A
公开(公告)日：1990-08-21
申请号：US264416
申请日：1988-10-31
申请人： Gerhard Miller , Jenoe Tihanyi , Peter Wehr
发明人： Gerhard Miller , Jenoe Tihanyi , Peter Wehr
IPC分类号： H01L29/68 , H01L21/322 , H01L29/08 , H01L29/32 , H01L29/739 , H01L29/74 , H01L29/744 , H01L29/78
CPC分类号： H01L21/3221 , H01L29/0834 , H01L29/32
摘要： Semiconductor structural elements with four regions of alternating conductivity type have a stored charge characteristic which becomes apparent as so-called "tail" current upon switching off. The tail current can be reduced by means of an anode-side emitter region containing damaged regions generated by laser bombardment which extend through a pn-junction formed between the anode-side emitter region and a central region up into the central region.
摘要翻译：具有交替导电类型的四个区域的半导体结构元件具有存储的电荷特性，其在关断时变为所谓的“尾”电流。可以通过包含由激光轰击产生的损坏区域的阳极侧发射极区域来减小尾电流，其延伸穿过在阳极侧发射极区域和中心区域之间形成的pn结，直到中心区域。

27. 发明授权

US4190850A MIS field effect transistor having a short channel length 失效
标题翻译： MIS场效应晶体管具有短的沟道长度
公开(公告)号：US4190850A
公开(公告)日：1980-02-26
申请号：US870216
申请日：1978-01-17
申请人： Jenoe Tihanyi , Guido Bell
发明人： Jenoe Tihanyi , Guido Bell
IPC分类号： H01L21/265 , H01L21/266 , H01L21/311 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7816 , H01L21/2652 , H01L21/266 , H01L21/31105 , H01L21/31111 , H01L29/1095 , H01L29/42368 , H01L29/66674 , H01L29/7801 , H01L29/7802 , H01L29/7824 , H01L29/78624 , H01L29/78657 , H01L29/0847 , H01L29/41766
摘要： A MIS field effect transistor having a source zone of a first impurity type formed in a semiconductor substrate immediately below one planar surface thereof, a drain zone of the first conductivity type in said substrate spaced from the source zone immediately below said one surface, a third zone, of said first impurity type in said substrate extending between said source and drain zones and extending deeper in said substrate than either said source or drain zones, a thin buried zone of the second conductivity type in said substrate spaced below and around the ends of said source zone, the region of said buried zone where it lies between said source and drain zones providing a channel whose length is only the thickness of the buried zone in the region where the buried zone reaches the substrate surface. A process for producing such a transistor is also disclosed.
摘要翻译：一种MIS场效应晶体管，其具有形成在其一个平面表面正下方的半导体衬底中的第一杂质型源极区，所述衬底中的第一导电类型的漏极区与所述一个表面正下方的源极区隔开，所述衬底中的所述第一杂质类型在所述源极和漏极区域之间延伸并且在所述衬底中比所述源极或漏极区域更深地延伸，所述衬底中的第二导电类型的薄掩埋区域在所述源极区，其位于所述源极和漏极区之间的所述掩埋区的区域，提供通道，其长度仅在掩埋区到达衬底表面的区域中的掩埋区的厚度。还公开了一种用于制造这种晶体管的工艺。

28. 发明授权

US4185293A Opto-electronic sensing apparatus and method 失效
标题翻译：光电传感装置及方法
公开(公告)号：US4185293A
公开(公告)日：1980-01-22
申请号：US725537
申请日：1976-09-22
申请人： Jenoe Tihanyi
发明人： Jenoe Tihanyi
IPC分类号： H01L27/146 , H01L27/14
CPC分类号： H01L27/14643
摘要： An opto-electronic sensor has an insulating substrate on which a plurality of x-lines of doped n (p) type conductivity semiconductor material are arranged. A light-permeable insulating layer covers the x-lines. A plurality of y-lines of electrically conductive material are then arranged over the insulating layer transversely to the x-lines. Sensor elements are formed at the crossover points of the x- and y-lines. A partial region of opposite conductivity type light sensitive material is arranged adjacent the x-line and beneath the y-line at the crossover point. This partial region forms a barrier-layer effect at a junction of the partial region with the doped semiconductor material of the x-lines.
摘要翻译：光电传感器具有绝缘基板，多个x线的n（p）型导电性半导体材料配置在绝缘基板上。透光绝缘层覆盖x线。然后在绝缘层上横向于x线布置多个y线导电材料。传感器元件形成在x线和y线的交叉点处。相反导电型感光材料的部分区域被布置在x线附近并且在交叉点处在y线下方。该部分区域在部分区域与x线的掺杂半导体材料的结处形成阻挡层效应。

29. 发明授权

US07453308B2 Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor 有权
标题翻译：具有负载晶体管的电路装置和用于驱动负载晶体管的电压限制电路和方法
公开(公告)号：US07453308B2
公开(公告)日：2008-11-18
申请号：US11057098
申请日：2005-02-11
申请人： Jenoe Tihanyi
发明人： Jenoe Tihanyi
IPC分类号： H03L5/00
CPC分类号： H03K17/302 , H03K17/0822
摘要： The invention relates to a circuit arrangement having connecting terminals (K1, K2) for application of a supply voltage (V+) and having a load transistor (M) for connecting a load (Z) to the supply voltage, said load transistor having a control terminal (G) and a first and second load terminal (D, S), the control terminal (G) of the load transistor (2) being coupled to a drive terminal (IN) for application of a drive signal (Sin). A voltage limiting circuit (10) is connected between one (D) of the load terminals and the drive terminal (G) of the transistor, a deactivation circuit (20) being provided, which is designed to deactivate the voltage limiting circuit (10) in a manner dependent on the supply voltage (V+).
摘要翻译：本发明涉及具有用于施加电源电压（V +）并具有用于将负载（Z）连接到电源电压的负载晶体管（M））的连接端子（K 1，K 2）的电路装置，所述负载晶体管具有控制端子（G）和第一和第二负载端子（D，S），负载晶体管（2）的控制端子（G）耦合到用于施加驱动信号（Sin）的驱动端子（IN）。电压限制电路（10）连接在负载端子的一个（D）和晶体管的驱动端子（G）之间，设置有去激活电压限制电路（10）的去激活电路（20）以取决于电源电压（V +）的方式。

30. 发明授权

US07301204B2 SOI component with increased dielectric strength and improved heat dissipation 有权
标题翻译： SOI元件具有增加的介电强度和改善的散热
公开(公告)号：US07301204B2
公开(公告)日：2007-11-27
申请号：US10943491
申请日：2004-09-17
申请人： Jenoe Tihanyi
发明人： Jenoe Tihanyi
IPC分类号： H01L29/72
CPC分类号： H01L29/7824 , H01L21/84 , H01L27/1203 , H01L29/0634 , H01L29/7393 , H01L29/78639 , H01L29/8611
摘要： A semiconductor component arrangement comprises a semiconductor substrate of a first conduction type, an insulation layer arranged on the substrate, and a semiconductor layer arranged on the insulation layer. A semiconductor component is formed in said semiconductor layer. The semiconductor component includes a first semiconductor zone of a first conduction type, a second semiconductor zone of a second conduction type adjoining the first semiconductor zone, and a third semiconductor zone which is doped more heavily than the second semiconductor zone and positioned at a distance from the first semiconductor zone. The semiconductor zone further comprises a fourth semiconductor zone of the second conduction type. The fourth semiconductor zone has a first section formed in the second semiconductor zone and a second section formed in the underlying substrate. The first section and the second section of the fourth semiconductor zone are electrically conductively connected to one another through the insulation layer.
摘要翻译：半导体元件布置包括第一导电类型的半导体衬底，布置在衬底上的绝缘层和布置在绝缘层上的半导体层。半导体元件形成在所述半导体层中。半导体部件包括第一导电类型的第一半导体区域，与第一半导体区域邻接的第二导电类型的第二半导体区域，以及比第二半导体区域更重掺杂的第三半导体区域，第一个半导体区。半导体区还包括第二导电类型的第四半导体区。第四半导体区域具有形成在第二半导体区域中的第一部分和形成在下面的基板中的第二部分。第四半导体区域的第一部分和第二部分通过绝缘层彼此导电连接。

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