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21. 发明授权

US08252629B2 Method for making a stackable package 有权
标题翻译：制作可堆叠包的方法
公开(公告)号：US08252629B2
公开(公告)日：2012-08-28
申请号：US12856401
申请日：2010-08-13
申请人： Kuo-Chung Yee , Meng-Jen Wang
发明人： Kuo-Chung Yee , Meng-Jen Wang
IPC分类号： H01L21/00 , H01L21/4763 , H01L21/44
CPC分类号： H01L23/49816 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2221/68327 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/06181 , H01L2224/12105 , H01L2224/131 , H01L2224/16225 , H01L2224/221 , H01L2224/2518 , H01L2225/06548 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/181 , H01L2924/00015 , H01L2924/00
摘要： The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized.
摘要翻译：本发明涉及一种制造可堆叠包装的方法。该方法包括以下步骤：（a）提供第一载体; （b）在所述第一载体上设置至少一个芯片; （c）形成模塑料以封装芯片; （d）移除第一载体; （e）形成第一再分布层和至少一个第一凸起; （f）提供第二载体; （g）设置在第二载体上; （h）去除芯片的一部分和模塑料的一部分; （i）形成第二重分布层; 和（j）移除第二载体。因此，第二再分配层使得可堆叠封装具有更多的灵活性被利用。

22. 发明授权

US07741152B2 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US07741152B2
公开(公告)日：2010-06-22
申请号：US11645040
申请日：2006-12-26
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A method of making a three-dimensional package, including: (a) providing a wafer; (b) forming at least one blind hole; (c) forming an isolation layer; (d) forming a conductive layer; (e) forming a dry film; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and the isolation layer, so as to expose the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.
摘要翻译：一种制造三维封装的方法，包括：（a）提供晶片; （b）形成至少一个盲孔; （c）形成隔离层; （d）形成导电层; （e）形成干膜; （f）用焊料填充盲孔; （g）去除干膜; （h）图案化导电层; （i）去除晶片的下表面的一部分和隔离层，以暴露导电层; （j）堆叠多个晶片，并进行回流处理; 和（k）切割堆叠的晶片，以便形成多个三维封装。因此，导电层的下端插入下晶片的焊料中，以增强导电层和焊料之间的接合，并且有效地降低了连接后三维封装的整体高度。

23. 发明申请

US20070172983A1 Three-dimensional package and method of making the same 审中-公开
标题翻译：三维包装及其制作方法
公开(公告)号：US20070172983A1
公开(公告)日：2007-07-26
申请号：US11645039
申请日：2006-12-26
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a three-dimensional package and a method of making the same. The three-dimensional package comprises a first wafer, at least one first hole, a first isolation layer, a first conductive layer, a first solder, a second wafer, at least one second hole, a second isolation layer, a second conductive layer, and a second solder. The first wafer has at least one first pad and a first protection layer exposing the first pad. The first hole penetrates the first wafer. The first isolation layer is disposed on the side wall of the first hole. The lower end of the first conductive layer extends below the surface of the first wafer. The first solder is disposed in the first hole, and is electrically connected to the first pad via the first conductive layer. The second wafer has at least one second pad and a second protection layer exposing the second pad. The second hole penetrates the second wafer. The second isolation layer is disposed on the side wall of the second hole. The lower end of the second conductive layer extends to below the surface of the second wafer and contacts the upper end of the first solder. The second solder is disposed in the second hole and is electrically connected to the second pad via the second conductive layer.
摘要翻译：本发明涉及三维包装及其制造方法。三维封装包括第一晶片，至少一个第一孔，第一隔离层，第一导电层，第一焊料，第二晶片，至少一个第二孔，第二隔离层，第二导电层，和第二焊料。第一晶片具有至少一个第一焊盘和暴露第一焊盘的第一保护层。第一个孔穿透第一个晶片。第一隔离层设置在第一孔的侧壁上。第一导电层的下端延伸到第一晶片的表面下方。第一焊料设置在第一孔中，并且经由第一导电层电连接到第一焊盘。第二晶片具有至少一个第二焊盘和暴露第二焊盘的第二保护层。第二孔穿透第二晶片。第二隔离层设置在第二孔的侧壁上。第二导电层的下端延伸到第二晶片的表面下方并接触第一焊料的上端。第二焊料设置在第二孔中，并通过第二导电层与第二焊盘电连接。

24. 发明授权

US07053488B2 Micro-mirror package 有权
标题翻译：微镜包装
公开(公告)号：US07053488B2
公开(公告)日：2006-05-30
申请号：US10905400
申请日：2004-12-31
申请人： Kuo-Chung Yee
发明人： Kuo-Chung Yee
IPC分类号： H01L29/40
CPC分类号： G02B26/0816 , H01L2224/48091 , H01L2224/73265 , H01L2924/01019 , H01L2924/00014
摘要： A micro-mirror package comprising a substrate, a bottom substrate, a cover substrate, a semiconductor chip, a first adhesive, a second adhesive, a plurality of wires and a lid is provided. The substrate has a circular wall. The bottom substrate is disposed on the substrate within the circular wall. The first adhesive is provided with first spacers for attaching the cover substrate to the semiconductor chip and setting the cover substrate and the semiconductor chip apart. The second adhesive is provided with second spacers for attaching the semiconductor chip to the bottom substrate and setting the semiconductor chip and the bottom substrate apart. The wires are used for electrically connecting the semiconductor chip and the substrate. The lid is disposed on top of the circular wall.
摘要翻译：提供了包括基板，底部基板，盖基板，半导体芯片，第一粘合剂，第二粘合剂，多根电线和盖子的微反射镜封装。基板具有圆形壁。底部基板设置在圆形壁内的基板上。第一粘合剂设置有用于将盖基板附接到半导体芯片并将盖基板和半导体芯片分开的第一间隔件。第二粘合剂设置有用于将半导体芯片附接到底部基板并将半导体芯片和底部基板分开的第二间隔件。电线用于电连接半导体芯片和基板。盖子设置在圆形壁的顶部。

25. 发明授权

US07033914B2 Method of making a package structure by dicing a wafer from the backside surface thereof 有权
标题翻译：通过从其背面切割晶片来制造封装结构的方法
公开(公告)号：US07033914B2
公开(公告)日：2006-04-25
申请号：US10919178
申请日：2004-08-16
申请人： Kuo-Chung Yee
发明人： Kuo-Chung Yee
IPC分类号： H01L21/301
CPC分类号： B81C1/00333 , H01L21/67092 , H01L21/78
摘要： The present invention relates to a method of making a package structure by dicing a wafer from the backside surface thereof comprising: (a) providing a first wafer having a active surface, a backside surface and a plurality of scribe lines defining a plurality of chips, wherein each chip has an annular body thereon; (b) dicing the first wafer from the active surface to form a reference coordinate; (c) providing a second wafer; (d) covering and joining the second wafer to the first wafer to form a plurality of cavities; and (e) dicing the corresponding positions of the scribe lines of the first wafer from the backside surface thereof according to the predetermined distance from the reference coordinate so as to form an individual package structure. As a result, the manufacture time is reduced.
摘要翻译：本发明涉及通过从其背面切割晶片来制造封装结构的方法，包括：（a）提供具有有源表面的第一晶片，背面和限定多个芯片的多个划线，其中每个芯片在其上具有环形体; （b）从活性表面切割第一晶片以形成参考坐标; （c）提供第二晶片; （d）将第二晶片覆盖并接合到第一晶片以形成多个空腔; 并且（e）根据与参考坐标的预定距离，从其背面切割第一晶片的划线的对应位置，以形成单独的封装结构。结果，制造时间缩短。

26. 发明申请

US20130277829A1 Method of Fabricating Three Dimensional Integrated Circuit 有权
标题翻译：制造三维集成电路的方法
公开(公告)号：US20130277829A1
公开(公告)日：2013-10-24
申请号：US13452636
申请日：2012-04-20
申请人： Kuo-Chung Yee , Chun Hui Yu
发明人： Kuo-Chung Yee , Chun Hui Yu
IPC分类号： H01L23/498 , H01L21/56
CPC分类号： H01L23/49811 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/498 , H01L23/49827 , H01L23/49894 , H01L24/10 , H01L24/81 , H01L24/97 , H01L2224/10 , H01L2224/16 , H01L2224/16225 , H01L2224/81 , H01L2224/81005 , H01L2224/97 , H01L2924/15311 , H01L2924/157 , H01L2924/15788 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.
摘要翻译：一种制造三维集成电路的方法包括在包装部件的第一侧上形成再分配层，在再分布层中形成保持室，将集成电路管芯附接在包装部件的第一侧上，其中互连凸块的集成电路管芯插入到保持室中，对集成电路管芯和封装部件进行回流处理，并在封装部件上形成封装层。

27. 发明申请

US20130020703A1 Method for Making a Stackable Package 审中-公开
标题翻译：制作可堆叠封装的方法
公开(公告)号：US20130020703A1
公开(公告)日：2013-01-24
申请号：US13560722
申请日：2012-07-27
申请人： Kuo-Chung Yee , Meng-Jen Wang
发明人： Kuo-Chung Yee , Meng-Jen Wang
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2221/68327 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/06181 , H01L2224/12105 , H01L2224/131 , H01L2224/16225 , H01L2224/221 , H01L2224/2518 , H01L2225/06548 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/181 , H01L2924/00015 , H01L2924/00
摘要： The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized.
摘要翻译：本发明涉及一种制造可堆叠包装的方法。该方法包括以下步骤：（a）提供第一载体; （b）在所述第一载体上设置至少一个芯片; （c）形成模塑料以封装芯片; （d）移除第一载体; （e）形成第一再分布层和至少一个第一凸起; （f）提供第二载体; （g）设置在第二载体上; （h）去除芯片的一部分和模塑料的一部分; （i）形成第二重分布层; 和（j）移除第二载体。因此，第二再分配层使得可堆叠封装具有更多的灵活性被利用。

28. 发明授权

US08288853B2 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US08288853B2
公开(公告)日：2012-10-16
申请号：US12615852
申请日：2009-11-10
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/05024 , H01L2224/05548 , H01L2224/05647 , H01L2224/05666 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2224/05099
摘要： A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.
摘要翻译：封装包括包括半导体本体，孔，隔离层，导电层和焊料的第一单元。半导体本体具有第一表面，其具有衬垫和暴露衬垫的保护层。孔穿透半导体本体。隔离层设置在孔的侧壁上。导电层覆盖焊盘，保护层的一部分和隔离层。导电层的下端延伸到半导体本体的第二表面的下方。焊料设置在孔中，并通过导电层与焊盘电连接。类似于第一单元并且堆叠在其上的第二单元包括延伸到第二半导体本体的第二表面下方并接触第一焊料的上端的第二导电层的下端。

29. 发明授权

US07642132B2 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US07642132B2
公开(公告)日：2010-01-05
申请号：US11584546
申请日：2006-10-23
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L21/44
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/05024 , H01L2224/05548 , H01L2224/05647 , H01L2224/05666 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2224/05099
摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.
摘要翻译：本发明涉及三维包装及其制造方法。该方法包括：（a）提供半导体本体; （b）在半导体本体中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）图案化导电层; （f）去除所述半导体主体的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （g）在导电层的下端形成焊料; （h）堆叠多个半导体体，进行回流处理; 和（i）切割堆叠的半导体本体，以便形成多个三维封装。因此，导电层的下端和其上的焊料被“插入”到由下半导体本体的导电层形成的空间中，以便增强导电层和焊料之间的接合，并且有效地减少加入后三维包装的整体高度。

30. 发明授权

US07528053B2 Three-dimensional package and method of making the same 有权
标题翻译：三维包装及其制作方法
公开(公告)号：US07528053B2
公开(公告)日：2009-05-05
申请号：US11645042
申请日：2006-12-26
申请人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
发明人： Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
IPC分类号： H01L21/46 , H01L21/4763
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/48145 , H01L2225/06506 , H01L2225/06524 , H01L2225/06541 , H01L2924/01019 , H01L2924/01078 , H01L2924/00012
摘要： A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.
摘要翻译：三维封装及其制造方法，包括提供晶片; 在晶片中形成至少一个盲孔; 在盲孔的侧壁上形成隔离层; 在隔离层上形成导电层; 在导电层上形成干膜; 用金属填充盲孔; 去除干膜，图案化导电层; 去除盲孔中的金属的一部分以形成空间; 去除所述晶片的所述第二表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; 在导电层的下端形成焊料，焊料的熔点低于金属; 堆叠多个晶片，并进行回流处理; 并切割堆叠的晶片，以形成三维封装。

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