专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07817068B2 Low power serial link bus architecture 有权
标题翻译：低功率串行总线架构
公开(公告)号：US07817068B2
公开(公告)日：2010-10-19
申请号：US11428247
申请日：2006-06-30
申请人： Maged Ghoneima , Muhammad M. Khellah , Vivek K. De
发明人： Maged Ghoneima , Muhammad M. Khellah , Vivek K. De
IPC分类号： H03M5/00
CPC分类号： H04L25/45
摘要： Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供一种利用多泵浦串行链路的总线架构，以及将编码和序列化到两个数据流的组合，以通过总线发送和接收串行数据流。编码和序列化的顺序取决于两个数据流的预期活动因素，并且被选择以减少平均能量耗散。描述和要求保护其他实施例。

22. 发明申请

US20080001793A1 LOW POWER SERIAL LINK BUS ARCHITECTURE 有权
标题翻译：低功率串行总线架构
公开(公告)号：US20080001793A1
公开(公告)日：2008-01-03
申请号：US11428247
申请日：2006-06-30
申请人： Maged Ghoneima , Muhammad M. Khellah , Vivek K. De
发明人： Maged Ghoneima , Muhammad M. Khellah , Vivek K. De
IPC分类号： H03M9/00
CPC分类号： H04L25/45
摘要： Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供一种利用多泵浦串行链路的总线架构，以及将编码和序列化到两个数据流的组合，以通过总线发送和接收串行数据流。编码和序列化的顺序取决于两个数据流的预期活动因素，并且被选择以减少平均能量耗散。描述和要求保护其他实施例。

23. 发明授权

US07280425B2 Dual gate oxide one time programmable (OTP) antifuse cell 有权
标题翻译：双栅氧化层一次可编程（OTP）反熔丝
公开(公告)号：US07280425B2
公开(公告)日：2007-10-09
申请号：US11239903
申请日：2005-09-30
申请人： Ali Keshavarzi , Fabrice Paillet , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Mohsen Alavi , Vivek K. De
发明人： Ali Keshavarzi , Fabrice Paillet , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Mohsen Alavi , Vivek K. De
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/146 , G11C17/165 , G11C29/027
摘要： A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.
摘要翻译：一次性可编程（OTP）单元包括耦合到反熔丝晶体管的存取晶体管。存取晶体管具有大于反熔丝晶体管的栅极氧化物厚度的栅极氧化物厚度，使得如果对反熔丝晶体管进行编程，则在存取晶体管的栅极/漏极结附近的电压不足以引起栅极氧化物存取晶体管分解。双栅氧化物OTP单元可以用于其中一次只编写一个OTP单元的阵列中。双栅氧化物OTP电池也可用于其中同时编程几个OTP电池的阵列中。

24. 发明授权

US07236005B1 Majority voter circuit design 有权
标题翻译：多数选民电路设计
公开(公告)号：US07236005B1
公开(公告)日：2007-06-26
申请号：US11053788
申请日：2005-02-09
申请人： Yibin Yee , James W. Tschanz , Muhammad M. Khellah , Vivek K. De
发明人： Yibin Yee , James W. Tschanz , Muhammad M. Khellah , Vivek K. De
IPC分类号： H03K19/23 , H03K19/003 , H03K19/20
CPC分类号： H03K19/23
摘要： A method and apparatus for performing majority voting is presented. The method selects pairs of inputs, performs AND and NOR operations on each pair of inputs to determine that each pair of inputs is both high or both low, yielding a quantity of “both high” pairs and a quantity of “both low” pairs, and compares the quantity of “both high” pairs against the quantity of “both low” pairs to determine the majority. The apparatus includes AND gates configured to receive pairs of values and NOR gates configured to receive the same pairs of values, with a connections between all AND gates and connections between all NOR gates. A summation element sums all AND gate outputs and all NOR gate outputs to determine the majority.
摘要翻译：提出了一种执行多数投票的方法和装置。该方法选择输入对，对每对输入进行AND和NOR运算，以确定每对输入均为高电平或两者均为低电平，产生“两高”对数量和“两低” 并将“两高”对数与“两低”对的数量进行比较，以确定多数。该装置包括被配置为接收配对的值对和配置成接收相同的值对的与非门，其中所有与门之间的连接和所有NOR门之间的连接。求和元素将所有与门输出和所有NOR门输出相加以确定大多数。

25. 发明授权

US07102951B2 OTP antifuse cell and cell array 有权
标题翻译： OTP反熔丝电池和电池阵列
公开(公告)号：US07102951B2
公开(公告)日：2006-09-05
申请号：US10979605
申请日：2004-11-01
申请人： Fabrice Paillet , Ali Keshavarzi , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Mohsen Alavi , Vivek K. De
发明人： Fabrice Paillet , Ali Keshavarzi , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Mohsen Alavi , Vivek K. De
IPC分类号： G11C17/18
CPC分类号： G11C17/146 , G11C17/16 , G11C17/18 , G11C29/027
摘要： Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.
摘要翻译：包括一次性可编程反熔丝电池的不同实施例。在一个实施例中，提供了包括反熔丝元件，高压器件和感测电路的电路。反熔丝元件在编程期间具有在感测/读取期间处于感测电压的电压提供端子和更高的编程电压。感测电路被配置为能够在编程期间对反熔丝元件进行编程，并且在感测期间感测反熔丝元件的状态。高电压设备耦合在反熔丝元件和感测电路之间，以在编程和感测期间将反熔断元件耦合到感测电路，并且在编程期间将感测电路与更高的编程电压保护性地屏蔽。

26. 发明授权

US06985380B2 SRAM with forward body biasing to improve read cell stability 有权
标题翻译：具有正向主体偏置的SRAM，以提高读取单元的稳定性
公开(公告)号：US06985380B2
公开(公告)日：2006-01-10
申请号：US10810093
申请日：2004-03-26
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Ali R. Farhang , Gunjan H. Pandya , Vivek K. De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Ali R. Farhang , Gunjan H. Pandya , Vivek K. De
IPC分类号： G11C11/412
CPC分类号： G11C11/419
摘要： A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.
摘要翻译：一种SRAM存储单元，包括交叉耦合的反相器，每个交叉耦合的反相器包括一个上拉晶体管，其中上拉晶体管在读取操作期间被正向偏置。正向主体偏置改善了存储单元的读取稳定性。描述和要求保护其他实施例。

27. 发明申请

US20090003108A1 SENSE AMPLIFIER METHOD AND ARRANGEMENT 有权
标题翻译： SENSE放大器方法和布置
公开(公告)号：US20090003108A1
公开(公告)日：2009-01-01
申请号：US11772151
申请日：2007-06-30
申请人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Nam Sung Kim , Vivek K. De
发明人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Nam Sung Kim , Vivek K. De
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/08 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2207/005
摘要： In one embodiment, a memory system having a selectable configuration for sense amplifiers is disclosed. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.
摘要翻译：在一个实施例中，公开了一种具有用于读出放大器的可选配置的存储器系统。存储器系统可以包括位单元和耦合到位单元和读出放大器的第一部分的开关模块。开关模块可以基于对读出放大器的第一部分的输入偏移电压的测试来连接，断开或将该位单元交叉耦合到读出放大器。类似的配置可以由读出放大器的第二部分来实现。该系统还可以包括用于配置开关模块的设置的编程器模块，并且可以包括列选择模块，以便基于要读取的位单元的列来将位单元耦合到读出放大器。还公开了其他实施例。

28. 发明授权

US07391640B2 2-transistor floating-body dram 有权
标题翻译： 2晶体管浮体电容
公开(公告)号：US07391640B2
公开(公告)日：2008-06-24
申请号：US11008666
申请日：2004-12-10
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C11/24 , G11C11/34
CPC分类号： G11C11/405 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
摘要翻译：动态随机存取存储器包括具有浮体晶体管和位线之间的电路的单元。控制电路的激活以在写入操作期间和在单元未被选择的时间期间在浮体和位线电压之间提供隔离。增加的隔离可以提高性能，例如，通过减少门到体耦合的需要和位线之间的电压摆幅的大小。

29. 发明授权

US07167397B2 Apparatus and method for programming a memory array 失效
标题翻译：用于编程存储器阵列的装置和方法
公开(公告)号：US07167397B2
公开(公告)日：2007-01-23
申请号：US11158518
申请日：2005-06-21
申请人： Fabrice Paillet , Ali Keshavarzi , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Mohsen Alavi , Vivek K. De , Tanay Karnik
发明人： Fabrice Paillet , Ali Keshavarzi , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Mohsen Alavi , Vivek K. De , Tanay Karnik
IPC分类号： G11C16/04
CPC分类号： G11C17/18
摘要： A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.
摘要翻译：提供了一种对存储器阵列进行编程的方法，包括通过相对于各个字线相互依次提供多个电压步骤来访问存储器阵列的多个字线，以及每个存储器阵列的多个位线访问相应字线的时间，对与同时访问的各个字和位线相对应的多个设备进行编程，每个设备通过断开设备的介电层进行编程，访问位线被排序，使得只有一个设备中的单个设备一次被编程。

30. 发明授权

US07123500B2 1P1N 2T gain cell 有权
标题翻译： 1P1N 2T增益电池
公开(公告)号：US07123500B2
公开(公告)日：2006-10-17
申请号：US10749734
申请日：2003-12-30
申请人： Yibin Ye , Dinesh Somasekhar , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien L. Lu , Vivek K. De
发明人： Yibin Ye , Dinesh Somasekhar , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien L. Lu , Vivek K. De
IPC分类号： G11C11/24
CPC分类号： G11C11/405
摘要： A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.
摘要翻译：双晶体管DRAM单元包括耦合到NMOS器件的NMOS器件和PMOS器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式