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21. 发明申请

US20050141701A1 Recharging terminal 失效
标题翻译：充电终端
公开(公告)号：US20050141701A1
公开(公告)日：2005-06-30
申请号：US10745415
申请日：2003-12-23
申请人： Kenji Nagai , Yoshihiro Matsuyama , Masakatsu Shimada , Masaya Fujino , Akio Shogen
发明人： Kenji Nagai , Yoshihiro Matsuyama , Masakatsu Shimada , Masaya Fujino , Akio Shogen
IPC分类号： H02J7/00 , H04M1/00 , H04M9/00 , H04M19/08
CPC分类号： H04M19/08 , H02J7/0045
摘要： Provided is an interterminal connection structure capable of eliminating the precipitate adhering to the terminal with the installation operation, securing the electrically connected state of the terminal between a pair of members, and easily accommodating to design changes in the spring load. In a cordless handset of a domestic telephone, the conductive state of the terminals employed in the electrical connection between this cordless handset and battery charger is made to contact in a mutually intersecting manner, and, in addition, the terminal on the battery charger side is made to rotate and move pursuant to the installation operation of the cordless handset, and the contact position is gradually moved while maintaining this contact state via such rotating movement. Thus, even if there is a precipitate on the terminals, such precipitate will be chipped off due to the contact movement (sliding), and a loose connection can thereby be prevented.
摘要翻译：提供了一种能够通过安装操作消除附着在端子上的沉淀物的互连连接结构，将端子的电连接状态确保在一对构件之间，并且易于容纳以设计弹簧载荷的变化。在家用电话的无绳电话机中，使得在该无绳手机和电池充电器之间的电连接中使用的终端的导电状态以相互交叉的方式接触，另外，电池充电器侧的端子根据无绳手机的安装操作使其旋转移动，并且通过这种旋转运动保持接触状态，接触位置逐渐移动。因此，即使在端子上存在沉淀，由于接触运动（滑动），这种沉淀物将被切掉，从而可以防止松动的连接。

22. 发明授权

US06788588B2 Asynchronous semiconductor memory device 有权
标题翻译：异步半导体存储器件
公开(公告)号：US06788588B2
公开(公告)日：2004-09-07
申请号：US10345353
申请日：2003-01-16
申请人： Kenji Nagai , Hirokazu Nagashima
发明人： Kenji Nagai , Hirokazu Nagashima
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1021 , G11C2207/2281
摘要： An asynchronous semiconductor memory device includes an output circuit, which outputs data read from a memory unit, and a high impedance control circuit. The high impedance circuit is connected to the output circuit, stores a burst completion address, and compares a present address with the burst completion address. The high impedance control circuit causes a data output terminal of the output circuit to enter a high impedance state when the present address substantially coincides with the burst completion address. Due to the high impedance control circuit, an exclusive terminal for high impedance control is not necessary.
摘要翻译：异步半导体存储器件包括输出从存储器单元读出的数据的输出电路和高阻抗控制电路。高阻抗电路连接到输出电路，存储突发完成地址，并将当前地址与突发完成地址进行比较。当本地址与突发完成地址基本一致时，高阻抗控制电路使输出电路的数据输出端进入高阻抗状态。由于高阻抗控制电路，不需要用于高阻抗控制的专用端子。

23. 发明授权

US5949823A Data communication system and radio IC card system 失效
标题翻译：数据通信系统和无线IC卡系统
公开(公告)号：US5949823A
公开(公告)日：1999-09-07
申请号：US928434
申请日：1997-09-12
申请人： Takashi Suga , Yoshihiko Hayashi , Ryouzou Yoshino , Kenji Nagai
发明人： Takashi Suga , Yoshihiko Hayashi , Ryouzou Yoshino , Kenji Nagai
IPC分类号： H04L27/227 , H04L27/00
CPC分类号： H04L27/2271
摘要： An arrangement to realize the functions of a radio card system in which power is transmitted to perform data communication. According to such arrangement, a delay line and a clock regenerating circuit such as PLL circuit which are previously necessary for demodulation by PSK are not necessary, and thus functions of data communication are realized by minimum hardware construction, size, cost and power consumption. Further, in a data communication system in which electric power transmission using a signal of a frequency fp and digital data communication using a carrier wave of a frequency fs are performed by radio, fs and fp are in the relationship of fs=fp/N (where N is an integer) and a phase shift P when the phase of the carrier wave is modulated by PSK is (M.times.360.degree.)/N (where M, N are integers and P is preferably not equal to 180.degree.).
摘要翻译：一种用于实现发送电力以执行数据通信的无线电卡系统的功能的装置。根据这样的配置，不需要延迟线和PLL电路等时钟再生电路，这是由PSK进行解调所必需的，因此通过最小的硬件结构，尺寸，成本和功率消耗来实现数据通信的功能。此外，在使用频率fp的信号的电力传输和使用频率fs的载波的数字数据通信通过无线电执行的数据通信系统中，fs和fp处于fs = fp / N（其中N是整数）和载波的相位被PSK调制的相移P是（M×360°）/ N（其中M，N是整数，P优选不等于180度）。

24. 发明授权

US5426784A Serial to parallel data converting circuit 失效
标题翻译：串行到并行数据转换电路
公开(公告)号：US5426784A
公开(公告)日：1995-06-20
申请号：US16532
申请日：1993-02-11
申请人： Atsumi Kawata , Hirotoshi Tanaka , Hiroki Yamashita , Kenji Nagai , Minoru Yamada , Nobuhiro Taniguchi
发明人： Atsumi Kawata , Hirotoshi Tanaka , Hiroki Yamashita , Kenji Nagai , Minoru Yamada , Nobuhiro Taniguchi
IPC分类号： G06F5/00 , H03M9/00 , G06F1/04
CPC分类号： H03M9/00
摘要： A shift register 10 receives serial data and outputs parallel data in synchronism with the timing of the serial data received. A shift register group 20, 21 receives bit outputs of the parallel data from the shift register 10. The number of bits of shift registers 20, 21 in the shift register group is set in a certain condition that corresponds to the bit outputs of the parallel data from the shift register 10. A plurality of coincidence circuits 107, 108 are provided, which detects agreement between a preset data starting pattern and the bit arrangement of the data in the shift register group. A selector 306 selects a set of parallel outputs from the shift register group according to the output signal from the coincidence circuits 107, 108. Thus only the shift register 10, performs high-speed operations at the same timing as the received serial data, and the other circuits operate at slower speeds whose timing is several times longer than that of the serial data received, thereby eliminating complex timing and averting difficulty control logic.
摘要翻译：移位寄存器10接收串行数据并且与所接收的串行数据的定时同步地输出并行数据。移位寄存器组20,21从移位寄存器10接收并行数据的位输出。移位寄存器组中的移位寄存器20,21的位数被设定在对应于并行的位输出的一定条件提供了多个符合电路107,108，其检测预设数据起始模式与移位寄存器组中的数据的位排列之间的一致性。选择器306根据来自符合电路107,108的输出信号从移位寄存器组中选择一组并行输出。因此，只有移位寄存器10在与所接收的串行数据相同的定时进行高速操作，以及其他电路以较慢的速度工作，其定时比接收的串行数据的时间长几倍，从而消除复杂的时序并避免难度控制逻辑。

25. 发明授权

US07738143B2 Copy-forgery-inhibited pattern or stamp image combined with image data based on user actions 失效
标题翻译：基于用户动作与图像数据组合的防伪图案或印记图像
公开(公告)号：US07738143B2
公开(公告)日：2010-06-15
申请号：US11610660
申请日：2006-12-14
申请人： Koichi Ishimoto , Masaki Kashiwagi , Nobuaki Miyahara , Takayuki Hirata , Yousuke Aoki , Asami Horiuchi , Kenji Nagai , Shuuko Kikuchi
发明人： Koichi Ishimoto , Masaki Kashiwagi , Nobuaki Miyahara , Takayuki Hirata , Yousuke Aoki , Asami Horiuchi , Kenji Nagai , Shuuko Kikuchi
IPC分类号： H04N1/00 , H04N1/387 , B41M3/14
CPC分类号： G03G21/043 , H04N1/00838 , H04N1/00883
摘要： The image data with the copy-forgery-inhibited pattern image added and an image area flag signal stored in the hard disk drive are inputted into a thinning filter. A thinning circuit does not perform thinning processing on these pieces of data and outputs the inputted image, as it is. The filter performs processing so that an image of a copy-forgery-inhibited pattern background part may be deleted. A selector selects an image signal not passing through the filter for a latent mark of the copy-forgery-inhibited pattern whose image area flag is set as “Character,” and select an image signal subjected to the processing by the filter for a copy-forgery-inhibited pattern background part whose image area flag is set as “Photograph.” By doing so, it is possible to perform low pass processing on only the copy-forgery-inhibited pattern background part and perform processing of making a latent-mark part emerge.
摘要翻译：添加了禁止复制伪造图案的图像数据和存储在硬盘驱动器中的图像区域标志信号被输入到稀疏滤波器中。稀疏电路不对这些数据进行稀疏化处理，直接输出输入的图像。过滤器执行处理，使得可以删除禁止复印伪造图案的图像的图像。选择器将图像区域标志设置为“字符”的复制防伪图案的潜在标记选择未通过滤光器的图像信号，并选择由滤色器进行处理的图像信号，其图像区域标记被设置为“照片”的伪造抑制图案背景部分。通过这样做，可以仅对禁止伪造的图案背景部分执行低通处理，并且执行使潜像标记部分出现。

26. 发明授权

US07706197B2 Storage device and control method of storage device 有权
标题翻译：存储设备的存储设备和控制方法
公开(公告)号：US07706197B2
公开(公告)日：2010-04-27
申请号：US11510077
申请日：2006-08-25
申请人： Kenji Nagai
发明人： Kenji Nagai
IPC分类号： G11C29/00 , G11C8/12
CPC分类号： G11C8/12
摘要： In a storage device having a redundancy remedy function in a block unit having a memory cells array divided in plural blocks, prior to the access operation to individual memory cells in the block, the block address BA for specifying a block is entered, and block redundancy is determined in the entered block address BA, and hence it is not necessary to determine input or redundancy of the block address BA on every occasion of the access operation. As a result, the time to the access operation start to the memory cell can be shortened, and the access speed is enhanced.
摘要翻译：在具有在多个块中划分的存储单元阵列的块单元中具有冗余补救功能的存储设备中，在对块内的各个存储单元的访问操作之前，输入用于指定块的块地址BA，并且块冗余在输入的块地址BA中确定，因此不需要在访问操作的每个场合确定块地址BA的输入或冗余。结果，可以缩短开始到存储单元的访问操作的时间，并且提高访问速度。

27. 发明申请

US20090323435A1 TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY 有权
标题翻译：减少半导体存储器的地址设置/保持时间
公开(公告)号：US20090323435A1
公开(公告)日：2009-12-31
申请号：US12341886
申请日：2008-12-22
申请人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
发明人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F1/10 , G11C7/109
摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.
摘要翻译：在本发明的存储装置中，响应于锁存控制信号对一系列信号进行锁存控制。设置锁存控制信号的锁存控制端子和分别输入一系列信号的多个信号端子。这里，分别提供多个锁存电路以对应于多个信号端子。多个锁存电路分别位于与其相关联的信号端子规定距离内并且距离锁存器控制端子在指定距离内。从信号端子到其相关联的锁存电路的信号传输的延迟可以被均衡，并且来自锁存控制端子的信号传输的延迟被输入到锁存电路，锁存控制端子用于执行锁存控制的信号被输入到锁存电路。这有助于减少信号的锁存特性的偏移。

28. 发明授权

US06385119B2 Internal supply voltage generating cicuit in a semiconductor memory device and method for controlling the same 有权
标题翻译：半导体存储器件中的内部电源电压生成电路及其控制方法
公开(公告)号：US06385119B2
公开(公告)日：2002-05-07
申请号：US09772076
申请日：2001-01-30
申请人： Isamu Kobayashi , Yoshiharu Kato , Kenji Nagai
发明人： Isamu Kobayashi , Yoshiharu Kato , Kenji Nagai
IPC分类号： G06F126
CPC分类号： G05F3/242
摘要： A method for controlling an internal supply voltage generating circuit reduces power consumption in an active mode. The internal supply voltage generating circuit includes a first voltage-drop regulator, which supplies a relatively large driving power to an internal circuit, and a second voltage-drop regulator, which supplies a relatively small driving power to the internal circuit. First, the second voltage-drop regulator is activated and the first voltage-drop regulator is inactivated in one of a stand-by mode and a power-down mode. Then, at least the first voltage-drop regulator is activated in an active mode, and the first voltage-drop regulator is inactivated in an active pause of the active mode. The first voltage-drop regulator is activated when the active pause is cancelled.
摘要翻译：用于控制内部电源电压发生电路的方法降低了活动模式下的功耗。内部电源电压产生电路包括向内部电路提供相对大的驱动功率的第一电压降调节器和向内部电路提供相对小的驱动功率的第二电压降调节器。首先，第二个电压降调节器被激活，第一个电压降调节器在待机模式和掉电模式之一被禁用。然后，至少第一电压降调节器在激活模式下被激活，并且第一电压降调节器在激活模式的活动暂停期间被非激活。当主动暂停被取消时，第一个电压降稳压器被激活。

29. 发明授权

US6128238A Direct sensing semiconductor memory device 有权
标题翻译：直接感应半导体存储器件
公开(公告)号：US6128238A
公开(公告)日：2000-10-03
申请号：US492005
申请日：2000-01-27
申请人： Kenji Nagai , Satoru Kawamoto , Takaaki Furuyama
发明人： Kenji Nagai , Satoru Kawamoto , Takaaki Furuyama
IPC分类号： G11C11/409 , G11C7/06 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/065
摘要： A direct sensing type semiconductor memory device combines read and write data bus lines in order to conserve real estate. The memory device includes a bit line pair and a sense amplifier connected between the lines of the bit line pair, and a data line pair. A first transistor is connected between a first potential and one of the data lines of the data line pair, and a gate of the first transistor is connected to one of the bit lines of the bit line pair. A second transistor is connected between the first potential and the other one of the data lines, and its gate is connected to the other of the bit lines. A switch circuit is connected between the data line pair and the bit line pair and transfers data from the data line pair to the bit line pair in accordance with a potential difference between the data line pair and the bit line pair.
摘要翻译：直接感测型半导体存储器件结合了读和写数据总线，以节省不动产。存储器件包括位线对和连接在位线对的线之间的读出放大器和数据线对。第一晶体管连接在数据线对的第一电位和数据线之一之间，第一晶体管的栅极连接到位线对的位线之一。第二晶体管连接在第一电位和另一个数据线之间，其栅极连接到另一条位线。开关电路连接在数据线对和位线对之间，并根据数据线对和位线对之间的电位差将数据从数据线对传送到位线对。

30. 发明授权

US5523622A Semiconductor integrated device having parallel signal lines 失效
标题翻译：具有并行信号线的半导体集成器件
公开(公告)号：US5523622A
公开(公告)日：1996-06-04
申请号：US533410
申请日：1995-09-25
申请人： Takashi Harada , Kazuhiro Yoshihara , Kazutaka Masuzawa , Kiyoshi Hayashi , Jun Kumazawa , Kenji Nagai , Masahiko Nishiuma , Chiyoshi Kamada
发明人： Takashi Harada , Kazuhiro Yoshihara , Kazutaka Masuzawa , Kiyoshi Hayashi , Jun Kumazawa , Kenji Nagai , Masahiko Nishiuma , Chiyoshi Kamada
IPC分类号： H01L23/12 , H01L23/13 , H01L23/498 , H01L23/66 , H01L39/02
CPC分类号： H01L23/13 , H01L23/49822 , H01L23/66 , H01L2224/16 , H01L2224/16235 , H01L2224/73253 , H01L2924/01079 , H01L2924/1305 , H01L2924/15153 , H01L2924/1517 , H01L2924/15173 , H01L2924/16195 , H01L2924/3011
摘要： For taking a characteristic impedance matching of signal transmission lines in a package which carries thereon a semiconductor chip with a very high-speed LSI formed thereon, there is provided a semiconductor integrated circuit device wherein one ends of signal transmission lines formed on a main surface of a package substrate are extended up to the position just under pads formed on a main surface of the semiconductor chip and are connected to the pads on the chip electrically through bump electrodes, while opposite ends of the signal transmission lines are extended to the outer peripheral portion of the main surface of the package substrate and outer leads are bonded thereto.
摘要翻译：为了在其上承载有非常高速LSI的半导体芯片的封装中采用信号传输线的特征阻抗匹配，提供了一种半导体集成电路器件，其中形成在主表面上的信号传输线的一端封装基板延伸到刚好在形成在半导体芯片的主表面上的焊盘下方的位置，并且通过凸块电极与芯片上的焊盘电连接，同时信号传输线的相对端延伸到外周部分的封装基板和外部引线的主表面接合。

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