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21. 发明申请

US20060036985A1 Compacting circuit responses 失效
公开(公告)号：US20060036985A1
公开(公告)日：2006-02-16
申请号：US11251664
申请日：2005-10-17
申请人： Subhasish Mitra , Kee Kim
发明人： Subhasish Mitra , Kee Kim
IPC分类号： G06F17/50 , H01L25/00 , H03K19/00
CPC分类号： G01R31/318566 , G01R31/3172 , G01R31/318547
摘要： Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.

22. 发明申请

US20060015786A1 System and shadow bistable circuits coupled to output joining circuit 失效
公开(公告)号：US20060015786A1
公开(公告)日：2006-01-19
申请号：US11218979
申请日：2005-09-02
申请人： Subhasish Mitra , Ming Zhang , Kee Kim
发明人： Subhasish Mitra , Ming Zhang , Kee Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318525
摘要： In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.

23. 发明授权

US06910173B2 Word voter for redundant systems 失效
标题翻译： Word选民冗余系统
公开(公告)号：US06910173B2
公开(公告)日：2005-06-21
申请号：US09925278
申请日：2001-08-08
申请人： Subhasish Mitra , Edward J. McCluskey
发明人： Subhasish Mitra , Edward J. McCluskey
IPC分类号： G06F11/18 , H03K19/23 , H03M13/43
CPC分类号： G06F11/184
摘要： The present invention provides a word voter for redundant systems with n modules wherein each of these n modules generates a word output. The word voter receives word outputs from each of the n modules. A voter decision is generated by the word voter utilizing a word basis of the word output of each of the n modules. The voter is based on a majority voting principle. The advantage of the present invention is that the word voter can be used to design redundant systems, such as, but not limited to, TMR systems, that are protected against common mode and multiple output failures. In addition, another advantage of the present invention is that is provides for a technique to efficiently design a TMR simplex system. The present invention provides a word voter for hardware systems.
摘要翻译：本发明提供了一种具有n个模块的冗余系统的单词选择器，其中这n个模块中的每一个产生一个单词输出。单词选择器从n个模块中的每一个接收单词输出。选民决定是由利用单词输出的单词输入单词生成的n个模块。选民是以多数投票原则为基础的。本发明的优点在于，词选词器可用于设计冗余系统，例如但不限于，TMR系统，其被保护不受共模和多输出故障的影响。此外，本发明的另一个优点是提供了一种有效地设计TMR单工系统的技术。本发明提供一种用于硬件系统的单词选择器。

24. 发明申请

US20050055613A1 Compacting circuit responses 有权
标题翻译：压缩电路响应
公开(公告)号：US20050055613A1
公开(公告)日：2005-03-10
申请号：US10656013
申请日：2003-09-05
申请人： Subhasish Mitra , Kee Kim
发明人： Subhasish Mitra , Kee Kim
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318547
摘要： A compactor has a reduced number of outputs and the ability to handle a higher number of errors and unknown logic values. The procedure for designing the matrix and the resulting compactor involves determining the number of unknown logic values that may be encountered and adding columns to the compactor matrix based on the number of errors. Basically, the number of possible combinations of scan in lines is determined. Then, additional columns are added for each possible combination of scan in lines. The number of columns that are added for each combination of scan in lines is equal to the number of errors plus one in one embodiment.
摘要翻译：压实机具有减少的输出数量和处理更多数量的错误和未知逻辑值的能力。设计矩阵和产生的压实机的过程涉及确定可能遇到的未知逻辑值的数量，并且基于错误数量向压实器矩阵添加列。基本上，确定线中扫描的可能组合的数量。然后，为行中扫描的每种可能组合添加其他列。为行中的扫描的每个组合添加的列数等于错误数量加上一个实施例中的列数。

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