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21. 发明授权

US06914324B2 Memory expansion and chip scale stacking system and method 有权
公开(公告)号：US06914324B2
公开(公告)日：2005-07-05
申请号：US10453398
申请日：2003-06-03
申请人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
发明人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
IPC分类号： H01L21/44 , H01L23/31 , H01L23/498 , H01L23/50 , H01L23/538 , H01L25/065 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36 , H01L23/02
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.

22. 发明授权

US07606048B2 Integrated circuit stacking system 有权
公开(公告)号：US07606048B2
公开(公告)日：2009-10-20
申请号：US10958584
申请日：2004-10-05
申请人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
发明人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
IPC分类号： H05K7/10 , H05K7/12
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2225/1094 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00012
摘要： The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).

23. 发明授权

US07256484B2 Memory expansion and chip scale stacking system and method 失效
标题翻译：内存扩展和芯片级堆叠系统及方法
公开(公告)号：US07256484B2
公开(公告)日：2007-08-14
申请号：US10963867
申请日：2004-10-12
申请人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
发明人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
IPC分类号： H01L23/02
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准被布置在柔性电路和IC封装之间，柔性电路的一部分放置在该IC封装上。形式标准提供了一种物理形式，允许在采用标准连接柔性电路设计时，在广泛的CSP封装系列中发现许多变化的封装尺寸。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载效应。这有利地改变了堆叠模块的DIMM板所呈现的阻抗特性。在优选实施例中，例如在逻辑控制下的FET多路复用器选择与填充在DIMM上的特定级别的堆叠模块相关联的特定数据线，以连接到存储器扩展系统中的控制芯片。

24. 发明授权

US07586758B2 Integrated circuit stacking system 有权
标题翻译：集成电路堆叠系统
公开(公告)号：US07586758B2
公开(公告)日：2009-09-08
申请号：US10958924
申请日：2004-10-05
申请人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
发明人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2225/1094 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00012
摘要： The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).
摘要翻译：本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。本发明可以利用各种尺寸和配置的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如DSBGA的裸片尺寸的封装。在根据本发明设计的优选实施例中，基体元件CSP集成电路和支撑元件CSP集成电路通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。连接到支撑元件的柔性电路的一部分折叠在基座元件上，以将支撑元件设置在基座元件上方，同时减小了总的占地面积。柔性电路在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。

25. 发明授权

US07495334B2 Stacking system and method 有权
标题翻译：堆叠系统和方法
公开(公告)号：US07495334B2
公开(公告)日：2009-02-24
申请号：US11197267
申请日：2005-08-04
申请人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle , Julian Dowden
发明人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle , Julian Dowden
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。在根据本发明的优选实施例设计的两高CSP堆叠或模块中，堆叠两个CSP，其中一个CSP设置在另一个之上。两个CSP与柔性电路连接。在柔性电路和堆叠中的CSP之间设置一个形式标准。形式标准可以采用许多配置，并且可以在柔性电路用于在具有两个或更多个组成CSP的堆叠模块中将CSP彼此连接的位置中使用。例如，在包括四个CSP的堆叠模块中，在优选实施例中采用三个形式标准，尽管可以使用更少的标准。形式标准提供导热物理形式，允许在广泛的CSP封装系列中找到许多变化的封装尺寸，同时采用标准连接柔性电路设计。

26. 发明授权

US07335975B2 Integrated circuit stacking system and method 有权
标题翻译：集成电路堆叠系统及方法
公开(公告)号：US07335975B2
公开(公告)日：2008-02-26
申请号：US10958934
申请日：2004-10-05
申请人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
发明人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2225/1094 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00012
摘要： The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).
摘要翻译：本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。本发明提供了用于将芯片级封装集成电路（CSP）或具有其他CSP的引线封装或者将单片或堆叠引线封装集成到节省PWB或其他板表面积的模块中的技术和结构。本发明可以利用各种尺寸和配置的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如DSBGA的裸片尺寸的封装。在根据本发明设计的优选实施例中，基体元件CSP和支撑元件CSP通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。柔性电路连接IC，并在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。

27. 发明授权

US06955945B2 Memory expansion and chip scale stacking system and method 有权
标题翻译：内存扩展和芯片级堆叠系统及方法
公开(公告)号：US06955945B2
公开(公告)日：2005-10-18
申请号：US10709732
申请日：2004-05-25
申请人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
发明人： Russell Rapport , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr. , Jeff Buchle
IPC分类号： H01L21/44 , H01L23/31 , H01L23/498 , H01L23/50 , H01L23/538 , H01L25/065 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36 , H01L21/48
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/50 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/0401
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard is disposed between the flex circuitry and the IC package over which a portion of the flex circuitry is laid. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In a preferred embodiment, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access. This favorably changes the impedance characteristics exhibited by a DIMM board populated with stacked modules. In a preferred embodiment, FET multiplexers for example, under logic control select particular data lines associated with particular levels of stacked modules populated upon a DIMM for connection to a controlling chip set in a memory expansion system.
摘要翻译：本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准被布置在柔性电路和IC封装之间，柔性电路的一部分放置在该IC封装上。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载效应。这有利地改变了堆叠模块的DIMM板所呈现的阻抗特性。在优选实施例中，例如在逻辑控制下的FET多路复用器选择与填充在DIMM上的特定级别的堆叠模块相关联的特定数据线，以连接到存储器扩展系统中的控制芯片。

28. 发明申请

US20060091529A1 High capacity thin module system and method 有权
标题翻译：大容量薄模块系统及方法
公开(公告)号：US20060091529A1
公开(公告)日：2006-05-04
申请号：US11231418
申请日：2005-09-21
申请人： James Wehrly , James Wilder , Paul Goodwin , Mark Wolfe
发明人： James Wehrly , James Wilder , Paul Goodwin , Mark Wolfe
IPC分类号： H01L23/34
CPC分类号： H05K1/189 , H05K1/0203 , H05K1/11 , H05K1/181 , H05K3/0061 , H05K2201/056 , H05K2201/09445 , H05K2201/10159 , H05K2201/1056 , H05K2201/10734 , H05K2203/1572
摘要： Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally conductive materials and includes a high thermal conductivity core or area that is disposed proximal to higher thermal energy devices such as an AMB when the flex circuit is brought about the substrate. Other variations include thermally-conductive clips that grasp respective ICs on opposite sides of the module to further shunt heat from the ICs. Preferred extensions from the substrate body or substrate core encourage reduced thermal variations amongst the integrated circuits of the module.
摘要翻译：灵活的电路填充有沿其主要侧面或其两侧设置的集成电路。沿柔性电路分布的触点提供模块与应用环境之间的连接。电路填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧，在衬底的一侧或两侧上具有一层或两层集成电路。衬底形式优选地由导热材料设计，并且当柔性电路绕在衬底上时，包括设置在较高热能器件（例如AMB）附近的高导热性芯或区域。其他变型包括将模块的相对侧上的相应IC夹持的导热夹子，以进一步从IC分流热量。来自衬底主体或衬底芯的优选延伸部件促进模块集成电路之间的热变化减小。

29. 发明申请

US20060033187A1 Rugged CSP module system and method 审中-公开
标题翻译：坚固的CSP模块系统和方法
公开(公告)号：US20060033187A1
公开(公告)日：2006-02-16
申请号：US10917216
申请日：2004-08-12
申请人： James Wilder , James Wehrly
发明人： James Wilder , James Wehrly
IPC分类号： H01L23/495
CPC分类号： H01L23/49833 , H01L23/49827 , H01L23/4985 , H01L2224/16 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H05K1/141 , H05K3/3436 , H05K2201/10378 , Y02P70/613 , H01L2224/0401
摘要： A rugged CSP module system and method are disclosed. In one embodiment of the present invention, a unitary mount is attached to a chip scale integrated circuit (CSP) to provide a CSP module with improved temperature cycle performance. In an exemplary system, the mount comprises a two metal layer flexible circuit attached to the CSP. Contacts are distributed along the flexible circuit for attachment to a printed circuit board (PCB). The body of the CSP then stands off from the PCB by the sum of the heights of the CSP contacts, the flex circuit, and the diameter of the contacts distributed along the flex circuit. Consequently, the forces arising from mismatched temperature coefficients of the PCB and CSP are distributed along a longer axis thus improving temperature cycle performance.
摘要翻译：公开了一种坚固的CSP模块系统和方法。在本发明的一个实施例中，单片机安装在芯片级集成电路（CSP）上，以提供具有改善的温度循环性能的CSP模块。在示例性系统中，安装件包括连接到CSP的两个金属层柔性电路。触点沿柔性电路分布，以连接到印刷电路板（PCB）。 CSP的主体然后通过CSP触点的高度，柔性电路和沿着柔性电路分布的触点的直径的总和从PCB脱离。因此，由PCB和CSP的不匹配的温度系数引起的力沿较长的轴分布，从而提高温度循环性能。

30. 发明申请

US20080094803A1 High Capacity Thin Module System and Method 有权
标题翻译：高容量薄模块系统和方法
公开(公告)号：US20080094803A1
公开(公告)日：2008-04-24
申请号：US11961477
申请日：2007-12-20
申请人： James Wehrly , James Wilder , Paul Goodwin , Mark Wolfe
发明人： James Wehrly , James Wilder , Paul Goodwin , Mark Wolfe
IPC分类号： H05K7/20
CPC分类号： H05K1/189 , H05K1/0203 , H05K1/11 , H05K1/181 , H05K3/0061 , H05K2201/056 , H05K2201/09445 , H05K2201/10159 , H05K2201/1056 , H05K2201/10734 , H05K2203/1572
摘要： Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally conductive materials and includes a high thermal conductivity core or area that is disposed proximal to higher thermal energy devices such as an AMB when the flex circuit is brought about the substrate. Other variations include thermally-conductive clips that grasp respective ICs on opposite sides of the module to further shunt heat from the ICs. Preferred extensions from the substrate body or substrate core encourage reduced thermal variations amongst the integrated circuits of the module.
摘要翻译：灵活的电路填充有沿其主要侧面或其两侧设置的集成电路。沿柔性电路分布的触点提供模块与应用环境之间的连接。电路填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧，在衬底的一侧或两侧上具有一层或两层集成电路。衬底形式优选地由导热材料设计，并且当柔性电路绕在衬底上时，包括设置在较高热能器件（例如AMB）附近的高导热性芯或区域。其他变型包括将模块的相对侧上的相应IC夹持的导热夹子，以进一步从IC分流热量。来自衬底主体或衬底芯的优选延伸部件促进模块集成电路之间的热变化减小。

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