专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20080116994A1 CIRCUIT TOPOLOGY FOR MULTIPLE LOADS 有权
标题翻译：多负载电路拓扑
公开(公告)号：US20080116994A1
公开(公告)日：2008-05-22
申请号：US11838238
申请日：2007-08-14
申请人： SHOU-KUO HSU , CHIA-NAN PAI , HSIAO-CHUAN TU
发明人： SHOU-KUO HSU , CHIA-NAN PAI , HSIAO-CHUAN TU
IPC分类号： H03H7/38
CPC分类号： H05K1/0246 , H05K1/0237 , H05K2201/09254 , H05K2201/10022
摘要： A circuit topology for multiple loads is provided. In an embodiment, the circuit topology includes a driving terminal (50), a first node (A), a first receiving terminal (10), and a second receiving terminal (20). The driving terminal is coupled to the first node via a main transmission line (11), the first node is respectively coupled to the first and second receiving terminals via a first branch transmission line (13) and a second branch transmission line (12). A first resistor (R2) is mounted on the second branch transmission line, a distance the signal travels from the driving terminal to the second receiving terminal via the main transmission line and the second branch transmission line is greater than a distance the signal travels from the driving terminal to the first receiving terminal via the main transmission and the first branch transmission line.
摘要翻译：提供了多个负载的电路拓扑。在一个实施例中，电路拓扑包括驱动终端（50），第一节点（A），第一接收终端（10）和第二接收终端（20）。驱动终端经由主传输线（11）耦合到第一节点，第一节点经由第一分支传输线（13）和第二分支传输线（12）分别耦合到第一和第二接收终端。第一电阻器（R 2）安装在第二分支传输线上，信号经由主传输线从驱动端到达第二接收端的距离，第二分支传输线大于信号从所述驱动终端经由所述主发送和所述第一分支传输线路发送到所述第一接收终端。

22. 发明申请

US20080040054A1 SYSTEM AND METHOD FOR ANALYZING LENGTHS OF BRANCHES OF SIGNAL PATHS 失效
标题翻译：用于分析信号分支长度的系统和方法
公开(公告)号：US20080040054A1
公开(公告)日：2008-02-14
申请号：US11768922
申请日：2007-06-27
申请人： SHOU-KUO HSU , CHIA-NAN PAI , CHENG-SHIEN LI
发明人： SHOU-KUO HSU , CHIA-NAN PAI , CHENG-SHIEN LI
IPC分类号： G01R15/00
CPC分类号： G06F17/5036 , G01R31/025 , G01R31/041
摘要： A system for analyzing lengths of branches of signal paths is disclosed. The system includes: a signal path naming module for naming all signal paths of a PCB; a signal path group selecting module for selecting a group of signal paths to be analyzed from the database; a signal path selecting module for selecting signal paths to be analyzed from the group of signal paths; a branch searching module for analyzing the selected signal paths, to search passive circuit components and external circuits connected to the selected signal paths for corresponding branches of the selected signal paths; a branch length calculating module for calculating a length of each branch; and a branch length comparing module for comparing each calculated branch length with a corresponding predefined maximal branch length to determine whether the calculated branch length is more than the predefined maximal branch length. A related method is also disclosed.
摘要翻译：公开了一种用于分析信号路径的分支长度的系统。该系统包括：用于命名PCB的所有信号路径的信号路径命名模块; 信号路径组选择模块，用于从数据库中选择要分析的一组信号路径; 信号路径选择模块，用于从信号路径组中选择要分析的信号路径; 用于分析所选择的信号路径的分支搜索模块，搜索与所选择的信号路径连接的无源电路组件和外部电路用于所选择的信号路径的相应分支; 分支长度计算模块，用于计算每个分支的长度; 以及分支长度比较模块，用于将每个计算的分支长度与相应的预定义的最大分支长度进行比较，以确定所计算的分支长度是否大于预定的最大分支长度。还公开了相关方法。

23. 发明申请

US20130048352A1 PRINTED CIRCUIT BOARD 失效
标题翻译：印刷电路板
公开(公告)号：US20130048352A1
公开(公告)日：2013-02-28
申请号：US13335996
申请日：2011-12-23
申请人： HUA-LI ZHOU , CHIA-NAN PAI , SHOU-KUO HSU
发明人： HUA-LI ZHOU , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： H05K1/09
CPC分类号： H05K1/0253
摘要： A printed circuit board includes a signal layer and a reference layer. The signal layer is covered with copper foil. A circuit topology for multiple loads is set on the signal layer. The circuit topology includes a driving terminal, a first signal receiving terminal, and a second signal receiving terminal. The driving terminal is connected to a node through a first transmission line. The node is connected to the first and second signal receiving terminals respectively through a second and a third transmission lines. A difference between lengths of the second and third transmission lines is greater than a product of a transmission speed and a rise time of signals from the driving terminal. The reference layer is covered with copper foil, and arranged under the signal layer. A region without copper foil is formed on the reference layer, under the second transmission line.
摘要翻译：印刷电路板包括信号层和参考层。信号层被铜箔覆盖。在信号层上设置多个负载的电路拓扑。电路拓扑包括驱动端子，第一信号接收端子和第二信号接收端子。驱动端子通过第一传输线连接到节点。节点分别通过第二和第三传输线连接到第一和第二信号接收终端。第二和第三传输线的长度之差大于来自驱动终端的信号的传输速度和上升时间的乘积。参考层用铜箔覆盖，并布置在信号层下面。在第二传输线下方，在参考层上形成没有铜箔的区域。

24. 发明申请

US20120331434A1 COMPUTING DEVICE AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINES 审中-公开
标题翻译：用于检查信号传输线的计算装置和方法
公开(公告)号：US20120331434A1
公开(公告)日：2012-12-27
申请号：US13483059
申请日：2012-05-30
申请人： YA-LING HUANG , CHIA-NAN PAI , SHOU-KUO HSU
发明人： YA-LING HUANG , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , H05K1/0296 , H05K3/0005 , H05K2201/09236
摘要： A computing device and a method reads design standards of signal transmission lines in a printed circuit board (PCB) layout file, and determines a minimum reference length of line segments of the signal transmission lines from the design standards. The device and method then selects a signal transmission line from a circuit board, and computes an actual length of each line segment of the selected signal transmission line. If each actual length is more than or equal to the minimum reference length, the device and method determines length design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is less than the minimum reference length, the device and method determines the length design of the signal transmission line does not satisfy the design standards.
摘要翻译：计算装置和方法读取印刷电路板（PCB）布局文件中的信号传输线的设计标准，并从设计标准确定信号传输线的线段的最小参考长度。然后，该装置和方法从电路板选择信号传输线，并计算所选信号传输线的每个线段的实际长度。如果每个实际长度大于或等于最小参考长度，则设备和方法确定所选信号传输线的长度设计满足设计标准。否则，如果实际长度小于最小参考长度，则设备和方法确定信号传输线的长度设计不符合设计标准。

25. 发明申请

US20120185819A1 SYSTEM AND METHOD FOR VERIFYING PCB LAYOUT 失效
标题翻译：用于验证PCB布局的系统和方法
公开(公告)号：US20120185819A1
公开(公告)日：2012-07-19
申请号：US13244625
申请日：2011-09-25
申请人： ZHENG SHAN , SHI-PIAO LUO , CHIA-NAN PAI , SHOU-KUO HSU
发明人： ZHENG SHAN , SHI-PIAO LUO , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.
摘要翻译：在使用计算装置验证印刷电路板（PCB）布局的方法中，从计算装置的存储装置获得PCB模拟文件，并且根据PCB仿真文件在显示装置上显示PCB图像。 PCB图像包括多个信号线和开关电压调节器节点（SVRN）。从PCB图像中选择要检查的SVRN，并搜索SVRN周围的所有信号线。该方法计算所选择的SVRN与所搜索的信号线之间的布局距离，并且生成图形窗口界面以定位其布局距离等于或小于最小距离的信号线。该方法通过将布局距离增加到最小距离来进一步修改定位信号线的布局以满足布局设计规范。

26. 发明申请

US20120167027A1 ELECTRONIC DEVICE AND METHOD FOR CHECKING LAYOUT DISTANCE OF A PRINTED CIRCUIT BOARD 审中-公开
标题翻译：电子设备和检查印刷电路板布局距离的方法
公开(公告)号：US20120167027A1
公开(公告)日：2012-06-28
申请号：US13172858
申请日：2011-06-30
申请人： YA-LING HUANG , SHI-PIAO LUO , CHIA-NAN PAI , SHOU-KUO HSU
发明人： YA-LING HUANG , SHI-PIAO LUO , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An electronic device and a method for checking layout distance of a printed circuit board (PCB) including presetting a checking condition to determine a reference layer. A high speed signal path is selected from a PCB design file, and a layer where the selected high speed signal path is located can be determined A reference layer of the determined layer is determined according to the checking condition, and a split line of the reference layer is determined. A shortest distance between each segment of the selected high speed signal path and the split line is calculated. If the shortest distance between a segment and the split line is less than the standard distance, layout of the segment is determined to be invalid.
摘要翻译：一种用于检查印刷电路板（PCB）的布局距离的电子设备和方法，包括预设检查条件以确定参考层。可以从PCB设计文件中选择高速信号路径，并且可以确定所选择的高速信号路径所在的层。根据检查条件确定确定层的参考层，并且确定参考的分割线层被确定。计算所选择的高速信号路径的每个段与分割线之间的最短距离。如果段与分割线之间的最短距离小于标准距离，则段的布局被确定为无效。

27. 发明申请

US20120048610A1 PRINTED CIRCUIT BOARD 有权
标题翻译：印刷电路板
公开(公告)号：US20120048610A1
公开(公告)日：2012-03-01
申请号：US12875156
申请日：2010-09-03
申请人： SHOU-KUO HSU , YUNG-CHIEH CHEN , HSIEN-CHUAN LIANG , WEN-LAING TSENG , SHEN-CHUN LI , CHIA-NAN PAI
发明人： SHOU-KUO HSU , YUNG-CHIEH CHEN , HSIEN-CHUAN LIANG , WEN-LAING TSENG , SHEN-CHUN LI , CHIA-NAN PAI
IPC分类号： H05K1/11
CPC分类号： H05K1/0251 , H05K1/115 , H05K2201/09836 , Y10T428/24917
摘要： A printed circuit board (PCB) includes two layers, two signal transmission traces, and a vertical interconnect access (via). The signal transmission traces are respectively arranged on the layers. The signal transmission traces are electrically connected to each other through the via. A centerline of the via with a vertical line of the layers form an acute angle θ, the angle θ is less than cos−1[(Lv2−Lt2)/(Lv2+Lt2)]. Wherein Lt is loss of the two signal transmitting traces in a unit length, and Lv is loss of the via in a unit length.
摘要翻译：印刷电路板（PCB）包括两层，两条信号传输路径和一条垂直互连接口（via）。信号传输迹线分别布置在层上。信号传输迹线通过通孔彼此电连接。具有垂直线的通孔的中心线形成锐角和角度;角度和角度; 小于cos-1 [（Lv2-Lt2）/（Lv2 + Lt2）]。其中Lt是以单位长度丢失两个信号传输迹线，并且Lv是单位长度中的通孔的损失。

28. 发明申请

US20120017191A1 COMPUTING DEVICE AND METHOD FOR CHECKING DISTANCES BETWEEN TRANSMISSION LINES AND ANTI-PADS ARRANGED ON PRINTED CIRCUIT BOARD 失效
标题翻译：用于检查传输线之间的距离的计算装置和方法以及在印刷电路板上安装的防平板
公开(公告)号：US20120017191A1
公开(公告)日：2012-01-19
申请号：US13085432
申请日：2011-04-12
申请人： HAN-LONG CHEN , SHI-PIAO LUO , CHENG-HSIEN LEE , CHIA-NAN PAI , SHOU-KUO HSU
发明人： HAN-LONG CHEN , SHI-PIAO LUO , CHENG-HSIEN LEE , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computing device and a method involves selection of one or more transmission lines from a printed circuit board (PCB) layout file, reading a transmission line from the one or more selected transmission lines, and determining neighboring anti-pads of the read transmission line in the PCB layout file. The computing device and method further determine an actual distance between the read transmission line and a neighboring anti-pad. If the actual distance is less than a preset standard distance, the computing device and method determine that the read transmission line and the neighboring anti-pad do not satisfy design requirements, and highlight the read transmission line and the neighboring anti-pad, to prompt a user to amend design of the read transmission line and the neighboring anti-pad.
摘要翻译：计算装置和方法包括从印刷电路板（PCB）布局文件中选择一条或多条传输线，从一条或多条所选传输线读取传输线，以及确定读传输线的相邻抗焊盘 PCB布局文件。计算设备和方法进一步确定读取传输线与相邻反焊盘之间的实际距离。如果实际距离小于预设的标准距离，则计算设备和方法确定读取传输线路和相邻的反焊盘不满足设计要求，并突出显示读取传输线路和相邻的反焊盘，以提示用户修改读取传输线的设计和相邻的反焊盘。

29. 发明申请

US20110094782A1 PRINTED CIRCUIT BOARD 有权
标题翻译：印刷电路板
公开(公告)号：US20110094782A1
公开(公告)日：2011-04-28
申请号：US12647395
申请日：2009-12-25
申请人： HUA-LI ZHOU , CHIA-NAN PAI , SHOU-KUO HSU
发明人： HUA-LI ZHOU , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： H05K1/16
CPC分类号： H05K1/0253 , H05K1/181 , H05K2201/09381 , H05K2201/0969 , H05K2201/10015 , H05K2201/10022 , H05K2201/10636 , Y02P70/611
摘要： A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ≈ 8  Wpad + 10  T 0.8  Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.
摘要翻译：印刷电路板包括信号平面和参考平面。信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。参考平面为通过无源元件和信号传输线传输的信号提供返回路径。在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。垂直于信号传输线的第一轴的长度满足以下等式：W 1≈8 Wpad + 10 T T W W W T T T + T，其中W pad是焊盘的宽度，Wtrace是传输线的宽度，T是焊盘的高度。

30. 发明申请

US20110055796A1 SYSTEM AND METHOD FOR REMOVING T-POINT ELEMENTS WITH UNUSED STUBS FROM A PCB LAYOUT DESIGN 失效
标题翻译：从PCB布局设计中删除未使用的STUBS的T点元素的系统和方法
公开(公告)号：US20110055796A1
公开(公告)日：2011-03-03
申请号：US12699839
申请日：2010-02-03
申请人： HAN-LONG CHEN , CHIA-NAN PAI , SHOU-KUO HSU
发明人： HAN-LONG CHEN , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and method for removing T-point elements with unused stubs from a printed circuit board (PCB) layout design obtains each signal line including one or more T-point elements in the PCB layout design, divides the obtained signal line into a plurality of lines according to the one or more T-point elements with unused stubs, and obtains properties of each of the plurality of lines. The system and method further deletes the original layout of the signal line and reconnects the plurality of lines according to the properties of each of the plurality of lines to generate a reconnected signal line, and outputs the reconnected signal line on a display device.
摘要翻译：用于从印刷电路板（PCB）布局设计中去除具有未使用的短截线的T点元件的系统和方法获得在PCB布局设计中包括一个或多个T点元件的每条信号线，将获得的信号线分成多个根据具有未使用短截线的一个或多个T点元素的线，并且获得多条线中的每一条的属性。该系统和方法进一步删除信号线的原始布局，并根据多条线中的每条线路的属性重新连接多条线路，以产生重新连接的信号线，并将重新连接的信号线输出到显示设备上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式