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21. 发明授权

US06804811B2 Process for layout of memory matrices in integrated circuits 有权
标题翻译：集成电路中存储矩阵布局的过程
公开(公告)号：US06804811B2
公开(公告)日：2004-10-12
申请号：US10254616
申请日：2002-09-25
申请人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
发明人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , G11C5/063
摘要： A memory module is formed on an integrated circuit by arranging memory cells in columns, and routing signal wires from module pins at an edge of the module to respective memory cells. The module pins are optimally positioned relative to the memory cells, and routing wires extend from the pins along routing lines to the cells. Buffer channels are defined between memory cells and orthogonal to the columns, and buffers are selectively inserted into the routing wires in the buffer channels by placing a plurality of buffers in each buffer channel. Signal wires to be buffered at a buffer channel are identified, and the signal wires are routed through each buffer channel so that (i) a signal wire to be buffered is re-routed to an input and output of a buffer, and (ii) all other signal wires are routed along their respective routing lines.
摘要翻译：存储器模块通过将存储器单元布置在列中而形成在集成电路上，并且将信号线从模块的边缘处的模块引脚路由到相应的存储器单元。模块引脚相对于存储单元最佳定位，并且布线从引脚沿着布线线延伸到单元。缓冲通道被定义在存储器单元之间并与列垂直的位置上，并且通过在每个缓冲通道中放置多个缓冲器将缓冲器选择性地插入到缓冲通道中的路由布线中。识别要在缓冲通道缓冲的信号线，并且信号线被路由到每个缓冲通道，使得（i）要缓冲的信号线被重新路由到缓冲器的输入和输出，以及（ii）所有其他信号线沿其各自的路由线路由。

22. 发明授权

US06526553B1 Chip core size estimation 有权
标题翻译：芯片尺寸估算
公开(公告)号：US06526553B1
公开(公告)日：2003-02-25
申请号：US09837492
申请日：2001-04-18
申请人： Alexander E. Andreev , Ranko Scepanovic , Ivan Pavisic
发明人： Alexander E. Andreev , Ranko Scepanovic , Ivan Pavisic
IPC分类号： G06E945
CPC分类号： G06F17/5072
摘要： A minimum core size of an integrated circuit chip is estimated for given parameters of an existing technology. The average wire length for the nets is calculated, and the centers of each cell are assigned to x,y coordinates to minimize wire length. The widths of routing channels between consecutive columns, and their associated core sizes are estimated based on the cell placement and the existing technology parameters. The minimum core size is identified from the estimated core sizes.
摘要翻译：对现有技术的给定参数估计集成电路芯片的最小核心尺寸。计算网络的平均线长度，并将每个单元格的中心分配给x，y坐标以最小化线长度。基于单元格放置和现有技术参数，估计连续列之间的路由通道的宽度及其相关的核心大小。从估计的核心尺寸确定最小核心尺寸。

23. 发明授权

US06075933A Method and apparatus for continuous column density optimization 失效
标题翻译：连续柱密度优化的方法和装置
公开(公告)号：US06075933A
公开(公告)日：2000-06-13
申请号：US906946
申请日：1997-08-06
申请人： Ivan Pavisic , Ranko Scepanovic , Alexander E. Andreev
发明人： Ivan Pavisic , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to optimize the cell density of the segments of columns on the IC. To optimize the segment or column density, the present columns densities are calculated, and the desired densities are determined. Then, the amount and the location of the of cell overload is found. The cells of the overloaded columns are spread out the neighboring columns. The reassignment of the cells are performed to minimize the distance, therefore the affect, of the relocation. To minimize the distance of relocation, the free spaces of the neighbors of the overloaded columns are identified, and the free spaces of the closest neighbors are used first, then the next closest, and so-on until the cells contributing to the overload are distributed.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。由于需要大量的单元和复杂的连接，所以必须正确地进行单元和电线程序的布置，以避免导线堵塞。本发明公开了优化IC上的列的单元密度的方法和装置。为了优化段或柱密度，计算出当前柱密度，并确定所需的密度。然后，发现电池过载量和位置。重载列的单元格分散在相邻列中。执行单元的重新分配以最小化搬迁的距离，因此最小化影响。为了最小化重定位的距离，识别重载列的邻居的空闲空间，并且首先使用最近的邻居的空闲空间，然后使用下一个邻近的空闲空间，并且如此分配，直到有助于过载的小区被分布。

24. 发明授权

US6070108A Method and apparatus for congestion driven placement 失效
标题翻译：堵塞驱动安置的方法和装置
公开(公告)号：US6070108A
公开(公告)日：2000-05-30
申请号：US906950
申请日：1997-08-06
申请人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
发明人： Alexander E. Andreev , Ivan Pavisic , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that wire routine be done correctly to avoid any congestion of wires. Placement of the cells and the routing of the wires to avoid congestion can be accomplished by determining congestion of various regions of the IC's after an initial placement of the cells and routing of the wires. The present invention discloses a method and apparatus to determine the congestion of the regions and a technique to increase the fictive heights (or, the "working height", or the "working size") of the cells for repeating the placement of the cells if the current placement and routing leads to congestion. The present invention provides for a method of defining regions and line segment. Then, each segment is analyzed to determine the ratio of the wire density of the segment to the wire capacity of the segment. If the ratio is greater than a predetermined value, then the fictive heights of the cells of the affected regions are increased and the placement is repeated.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。由于需要大量的单元和复杂的连接，因此必须正确地进行线路程序，以避免导线的拥塞。可以通过在单元的初始放置和导线的布线之后确定IC的各个区域的拥塞来实现单元的放置和导线的路由以避免拥塞。本发明公开了一种确定区域拥挤的方法和装置，以及增加用于重复放置细胞的细胞的假想高度（或“工作高度”或“工作大小”）的技术，如果当前的布局和路由导致拥塞。本发明提供了一种定义区域和线段的方法。然后，分析每个段以确定段的线密度与段的线容量的比率。如果比率大于预定值，则影响区域的细胞的假想高度增加并重复放置。

25. 发明授权

US6058254A Method and apparatus for vertical congestion removal 失效
标题翻译：垂直堵塞消除的方法和装置
公开(公告)号：US6058254A
公开(公告)日：2000-05-02
申请号：US906948
申请日：1997-08-06
申请人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to reduce or to eliminate cell placement and wire routing congestion. To reduce vertical congestion, the cells are moved from congested regions to uncongested regions. The present invention discloses techniques of defining regions as pieces and columns, determining the level of congestion in the regions, and the methods of moving the cells to different columns to reduce congestion while minimizing affects to wire routing. The movement of the cells to other columns may create overlapping of the cells or overloading of the columns. The present invention also discloses the methods to resolve the overlapping and overloading problems.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。由于需要大量的单元和复杂的连接，所以必须正确地进行单元和电线程序的布置，以避免导线堵塞。本发明公开了减少或消除小区布置和布线拥塞的方法和装置。为了减少垂直拥堵，细胞从拥挤的区域移动到非占据区域。本发明公开了将区域定义为片段和列，确定区域中的拥塞水平的技术以及将小区移动到不同列以减少拥塞同时最小化对线路布线的影响的方法。细胞到其他柱的运动可能造成细胞重叠或柱的重载。本发明还公开了解决重叠和重载问题的方法。

26. 发明授权

US6000038A Parallel processing of Integrated circuit pin arrival times 失效
标题翻译：并联处理集成电路引脚到达时间
公开(公告)号：US6000038A
公开(公告)日：1999-12-07
申请号：US964784
申请日：1997-11-05
申请人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. Because of the large number of cells and nets of an IC, the process of determining IC delay of an IC design requires a lot of time. The present invention discloses a method and apparatus for determining the IC delay quickly by using multiple processors and analyzing multiple pins simultaneously. Also disclosed is the method of ordering the pins to allow the application of the parallel processing technique.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。 IC的设计需要满足实际的限制，例如最小化电路面积，最小化电路内的电线长度，以及使IC执行其功能所需的时间最小化，称为IC延迟。由于IC的单元和网络数量众多，因此确定IC设计IC延迟的过程需要大量的时间。本发明公开了一种通过使用多个处理器并同时分析多个引脚来快速确定IC延迟的方法和装置。还公开了排列引脚以允许应用并行处理技术的方法。

27. 发明授权

US5859782A Efficient multiprocessing for cell placement of integrated circuits 失效
标题翻译：集成电路单元放置的高效多处理
公开(公告)号：US5859782A
公开(公告)日：1999-01-12
申请号：US798648
申请日：1997-02-11
申请人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5072
摘要： A method for maximizing effectiveness of parallel processing, using multiple processors, to achieve an optimal cell placement layout of a core area of an integrated chip is disclosed. The method requires the core area to be divided into preferably a grid of rectangular regions. Then, the rectangular region is sequenced such that each region of the sequence is not adjacent to the previous or the next region of the sequence, and is sufficiently far from the previous and from the next region of the sequence such that when multiple processors are assigned to consecutive regions of the sequence to perform cell placement algorithms, area-conflicts are minimized eliminating the need to limit the distances the cells may be moved.
摘要翻译：公开了一种最大化使用多个处理器的并行处理的有效性以实现集成芯片的核心区域的最佳单元布局布局的方法。该方法需要将核心区域优选地分成矩形区域的格子。然后，对矩形区域进行排序，使得序列的每个区域不与序列的先前或下一个区域相邻，并且距离序列的前一个和下一个区域足够远，使得当分配多个处理器时到序列的连续区域以执行细胞放置算法，最小化区域冲突，从而不需要限制细胞可能被移动的距离。

28. 发明授权

US07548844B2 Sequential tester for longest prefix search engines 失效
标题翻译：最长前缀搜索引擎的顺序测试器
公开(公告)号：US07548844B2
公开(公告)日：2009-06-16
申请号：US11706943
申请日：2007-02-13
申请人： Alexander E. Andreev , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Anatoli A. Bolotov
IPC分类号： G06F9/45
CPC分类号： G01R31/31917 , Y10S707/99933
摘要： The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.
摘要翻译：本发明涉及一种用于最长前缀搜索引擎的顺序测试器。测试器可以包括最长的前缀搜索引擎，用于向最长的前缀搜索引擎提供几乎随机的输入命令的输入生成器，并输出可以表示最长前缀搜索引擎的搜索表的浮动矩形，编码模块用于向最长前缀搜索引擎提供地址和前缀信息，用于向最长前缀搜索引擎提供数据信息的映射模块，用于执行超级搜索操作的超级搜索引擎和用于计算最长前缀搜索引擎的预测输出的分析器并将预测输出与由最长前缀搜索引擎计算的实际输出进行比较。

29. 发明授权

US07430694B2 Memory BISR architecture for a slice 有权
标题翻译：内存BISR架构为一片
公开(公告)号：US07430694B2
公开(公告)日：2008-09-30
申请号：US11038698
申请日：2005-01-20
申请人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
IPC分类号： G11C29/00 , G06F12/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： The present invention provides a memory BISR architecture for a slice. The architecture includes (1) a plurality of physical memory instances; (2) a Mem_BIST controller, communicatively coupled to the plurality of physical memory instances, for testing the plurality of physical memory instances; (3) a FLARE module, communicatively coupled to the Mem_BIST controller, including a scan chain of registers for storing test results of the plurality of physical memory instances, each of the plurality of physical memory instances M_i being assigned one FLARE bit f_i, i=1, 2, . . . , n, the FLARE module being used by the Mem_BIST controller to scan in an error vector F=(f—1, f—2, . . . , f_n); (4) a BISR controller, communicatively coupled to the FLARE module, a ROM module and a REPAIR_CONFIGURATION module, for scanning out the error vector F from the FLARE module to computer a repair configuration vector R=(r—1, r—2, . . . , r_n); and (5) a FUSE module, communicatively coupled to the BISR controller and the REPAIR_CONFIGURATION module, for storing the repair configuration vector R. The REPAIR_CONFIGURATION module, communicatively coupled to the plurality of physical memory instances M_i and an integrated circuit design D, includes switch module instances S for switching among the plurality of physical memory instances in accordance with the repair configuration vector R. The ROM module stores a vector U indicating usage of the plurality of physical memory instances M_i by the integrated circuit design D.
摘要翻译：本发明提供了一种用于切片的存储器BISR架构。该架构包括（1）多个物理存储器实例; （2）通信地耦合到所述多个物理存储器实例的用于测试所述多个物理存储器实例的Mem_BIST控制器; （3）FLARE模块，通信地耦合到所述Mem_BIST控制器，包括用于存储所述多个物理存储器实例的测试结果的寄存器扫描链，所述多个物理存储器实例M_i中的每一个被分配一个FLARE位f_i，i = 1，2，... 。。，n，由Mem_BIST控制器使用的FLARE模块以错误向量F =（f 1 - 1，f 2 - ，...，f_n）进行扫描; （4）通信地耦合到FLARE模块的BISR控制器，ROM模块和REPAIR_CONFIGURATION模块，用于从FLARE模块向计算机扫描出错误向量F，修复配置向量R =（r - > 1，r 2，...，r_n）; 和（5）通信地耦合到BISR控制器和REPAIR_CONFIGURATION模块的FUSE模块，用于存储修复配置向量R.通信地耦合到多个物理存储器实例M_i和集成电路设计D的REPAIR_CONFIGURATION模块包括开关模块实例S，用于根据修复配置向量R在多个物理存储器实例之间切换.ROM模块通过集成电路设计D存储指示多个物理存储器实例M_i的使用的向量U。

30. 发明授权

US07328382B2 Memory BISR controller architecture 失效
标题翻译：内存BISR控制器架构
公开(公告)号：US07328382B2
公开(公告)日：2008-02-05
申请号：US11270077
申请日：2005-11-09
申请人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Sergey V. Gribok , Anatoli A. Bolotov
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/44 , G06F11/00 , G11C29/4401 , G11C29/72
摘要： The present invention provides an architecture of a memory Built-In Self Repair (BISR) controller for connecting to N memory instances, where N is a positive integer greater than 1. The architecture includes N groups of data ports, N BISR_SUBMOD modules for connecting to the N memory instances, and a CLK_IN input port and a BISR_IN input port for setting configuration of the memory BISR controller. Each of the N groups of data ports includes (1) a PHY_IN output port for connecting to input of a corresponding memory instance; (2) a PHY_OUT input port for connecting to output of the corresponding memory instance; (3) a LOG_IN input port for sending signals to the corresponding memory instance; and (4) a LOG_OUT output port for receiving signals from the corresponding memory instance. Each of the N BISR_SUBMOD modules includes a flip-flop, a first mux and a second mux. The CLK_IN input port is connected to clock inputs of all N flip-flops of the memory BISR controller. The BISR_IN input port is connected to data input of a first flip-flop, and output of a K-th flip-flop is connected to input of a (K+1)-th flip-flop, K=1, 2, . . . , N-1. When at least one of the N memory instances is defective, the memory BISR controller may reconfigure connections among the N memory instances to use other memory instance(s) instead of the defective memory instance(s).
摘要翻译：本发明提供了一种用于连接到N个存储器实例的存储器内置自修复（BISR）控制器的架构，其中N是大于1的正整数。该架构包括N组数据端口，N个BISR_SUBMOD模块用于连接到 N个内存实例，以及用于设置内存BISR控制器配置的CLK_IN输入端口和BISR_IN输入端口。 N组数据端口中的每一个包括（1）用于连接到相应存储器实例的输入的PHY_IN输出端口; （2）用于连接到相应存储器实例的输出的PHY_OUT输入端口; （3）用于向相应的存储器实例发送信号的LOG_IN输入端口; 和（4）用于从相应的存储器实例接收信号的LOG_OUT输出端口。 N BISR_SUBMOD模块中的每一个包括触发器，第一多路复用器和第二复用器。 CLK_IN输入端口连接到存储器BISR控制器的所有N个触发器的时钟输入。 BISR_IN输入端口连接到第一触发器的数据输入，第K触发器的输出连接到第（K + 1）个触发器的输入，K = 1,2。。。，N-1。当N个存储器实例中的至少一个存在缺陷时，存储器BISR控制器可以重新配置N个存储器实例之间的连接以使用其他存储器实例而不是缺陷存储器实例。

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