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21. 发明申请

US20130051099A1 Inverter Device 有权
标题翻译：变频器
公开(公告)号：US20130051099A1
公开(公告)日：2013-02-28
申请号：US13638287
申请日：2011-03-31
申请人： Tetsuro Tateyama , Seiji Funaba , Yasuo Noto , Koichi Yahata , Hiroki Shimano
发明人： Tetsuro Tateyama , Seiji Funaba , Yasuo Noto , Koichi Yahata , Hiroki Shimano
IPC分类号： H02M7/537
CPC分类号： H02M7/5387
摘要： An inverter device includes: an inverter circuit which includes an upper-arm-use first switching element (328U to 328W) and a lower-arm-use second switching element (330U to 330W); a control circuit (319) which outputs a first signal which is an ON/OFF command for the first switching element and a second signal which is an ON/OFF command for the second switching element respectively; a first drive circuit (610U to 610W) which performs ON/OFF driving of the first semiconductor switching element based on the ON/OFF command which is the first signal; a second drive circuit (611U to 611W) which performs ON/OFF driving of the second semiconductor switching element based on the ON/OFF command which is the second signal; and a signal switching part (616U to 616W) which directly inputs the first and second signals outputted from the control circuit to the corresponding first and second drive circuits respectively when at least one of the first and second signals is an OFF command, and interrupts inputting of the first signal to the first drive circuit and inputting of the second signal to the second drive circuit and inputs a third signal which is an OFF command to the first and second drive circuits when both the first and second signals are ON commands.
摘要翻译：逆变器装置包括：包括上臂使用的第一开关元件（328U至328W）和下臂用第二开关元件（330U至330W）的逆变器电路; 输出作为第一开关元件的ON / OFF指令的第一信号和作为第二开关元件的ON / OFF指令的第二信号的控制电路（319）基于作为第一信号的ON / OFF命令，执行第一半导体开关元件的ON / OFF驱动的第一驱动电路（610U〜610W）基于作为第二信号的ON / OFF命令进行第二半导体开关元件的ON / OFF驱动的第二驱动电路（611U〜611W）以及当第一和第二信号中的至少一个是OFF命令时，分别直接将从控制电路输出的第一和第二信号输入到相应的第一和第二驱动电路的信号切换部分（616U至616W），并且中断输入的第一信号输入到第一驱动电路，并将第二信号输入到第二驱动电路，并且当第一和第二信号都是ON命令时，将作为OFF命令的第三信号输入到第一和第二驱动电路。

22. 发明授权

US08274841B2 Semiconductor signal processing device 有权
公开(公告)号：US08274841B2
公开(公告)日：2012-09-25
申请号：US13354028
申请日：2012-01-19
申请人： Hiroki Shimano , Kazutami Arimoto
发明人： Hiroki Shimano , Kazutami Arimoto
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C8/04 , G11C8/12 , G11C11/1675 , G11C11/405 , G11C11/4076 , G11C11/5607 , G11C15/02 , G11C15/046 , G11C2211/4016 , H01L27/0207 , H01L27/1203
摘要： A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area.

23. 发明申请

US20110085364A1 SEMICONDUCTOR SIGNAL PROCESSING APPARATUS 失效
标题翻译：半导体信号处理设备
公开(公告)号：US20110085364A1
公开(公告)日：2011-04-14
申请号：US12900915
申请日：2010-10-08
申请人： Hiroki Shimano , Kazutami Arimoto
发明人： Hiroki Shimano , Kazutami Arimoto
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A pair of operator cells each having a series-coupled circuit of first and second transistors is used as a storage unit. To-be-retrieved data and retrieval data are respectively stored in the first and second transistors, and mutually complementary data items are stored in the operator cells of the storage unit. The operator cells supply currents according to the result of an AND operation between the stored data items to corresponding bit lines, and the read data from the storage unit corresponds to the result of an EXOR operation between the retrieval data and the to-be-retrieved data. The currents flowing in the corresponding bit lines are amplified with sense amplifier circuits to drive local match lines. In the individual sub-blocks of an operator cell array, data items having different pattern lengths can be stored. The potentials of the local match lines are selected according to the data pattern lengths, and match retrieval is performed for the data items having the different pattern lengths.
摘要翻译：每个具有第一和第二晶体管的串联耦合电路的一对操作单元被用作存储单元。待检索的数据和检索数据分别存储在第一和第二晶体管中，相互补充的数据项存储在存储单元的操作员单元中。操作员单元根据存储的数据项与对应的位线之间的AND运算结果来提供电流，并且来自存储单元的读取数据对应于检索数据和待检索的EXOR操作的结果数据。在对应位线中流动的电流用读出放大器电路放大，以驱动局部匹配线。在操作员单元阵列的各个子块中，可以存储具有不同图案长度的数据项。根据数据图案长度选择局部匹配线的电位，并且对具有不同图案长度的数据项执行匹配检索。

24. 发明授权

US07738312B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07738312B2
公开(公告)日：2010-06-15
申请号：US12000343
申请日：2007-12-12
申请人： Hiroki Shimano , Fukashi Morishita , Kazutami Arimoto
发明人： Hiroki Shimano , Fukashi Morishita , Kazutami Arimoto
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/12 , G11C7/18 , G11C11/405 , G11C11/4094 , G11C11/4097 , G11C2211/4016 , H01L21/84 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.
摘要翻译：一个存储单元由第一端口存取晶体管，第二端口存取晶体管和与这些存取晶体管共同耦合的存储晶体管形成。第一端口存取晶体管耦合到存储晶体管的第一电极，第二端口存取晶体管耦合到存储晶体管的第三电极。当分别选择第一和第二端口字线时，这些第一和第二端口存取晶体管进入选择状态，以将相应的存储晶体管的相应的第二和第三电极分别耦合到第一和第二端口位线。可以提供一种双端口存储单元，其可扩展性可以在一个过程中跟随小型化。

25. 发明授权

US07248495B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07248495B2
公开(公告)日：2007-07-24
申请号：US11397811
申请日：2006-04-05
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/24
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑合并的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

26. 发明授权

US07046543B2 Semiconductor memory device with improved data retention characteristics 失效
标题翻译：具有改进的数据保留特性的半导体存储器件
公开(公告)号：US07046543B2
公开(公告)日：2006-05-16
申请号：US10922936
申请日：2004-08-23
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/24
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑合并的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

27. 发明授权

US06487105B2 Test circuit for semiconductor integrated circuit which detects an abnormal contact resistance 失效
标题翻译：用于检测异常接触电阻的半导体集成电路的测试电路
公开(公告)号：US06487105B2
公开(公告)日：2002-11-26
申请号：US09741998
申请日：2000-12-22
申请人： Toshinori Morihara , Hiroki Shimano
发明人： Toshinori Morihara , Hiroki Shimano
IPC分类号： G11C1124
CPC分类号： G11C29/50 , G11C5/063 , G11C11/401
摘要： There is provided a semiconductor integrated circuit having a multi level interconnect structure comprising: a first wiring connected to a transistor region formed in a semiconductor substrate; an interlayer dielectric formed on this topography; first and second contacts formed in the interlayer dielectric; and a second wiring connected electrically to the first wiring via the first and second contacts, this circuit further including switching means, connected to said first and second wirings respectively, for feeding a high potential and a low potential alternately.
摘要翻译：提供一种具有多电平互连结构的半导体集成电路，包括：连接到形成在半导体衬底中的晶体管区域的第一布线; 在该形貌上形成的层间电介质; 在层间电介质中形成的第一和第二触点; 以及经由第一和第二触点与第一布线电连接的第二布线，该电路还包括分别连接到所述第一和第二布线的开关装置，用于交替地馈送高电位和低电位。

28. 发明授权

US06486493B2 Semiconductor integrated circuit device having hierarchical test interface circuit 失效
公开(公告)号：US06486493B2
公开(公告)日：2002-11-26
申请号：US09942827
申请日：2001-08-31
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： H01L2358
CPC分类号： G11C29/48
摘要： A plurality of test interface circuits are disposed in correspondence with a plurality of DRAM cores. An upper test interface circuit transmits a test control signal or the like supplied from the outside to each of or one of the plurality of test interface circuits in accordance with a memory core selection signal. When all of the DRAM cores are designated as targets of an operation test, test output data from the DRAM cores is compared with each other by a data comparing circuit and is outputted as judge flag data reflecting the result of the comparison to the outside.

29. 发明授权

US6067260A Synchronous semiconductor memory device having redundant circuit of high repair efficiency and allowing high speed access 失效
标题翻译：同步半导体存储器件具有高修复效率和允许高速访问的冗余电路
公开(公告)号：US6067260A
公开(公告)日：2000-05-23
申请号：US195194
申请日：1998-11-18
申请人： Tsukasa Ooishi , Shigeki Tomishima , Hiroki Shimano
发明人： Tsukasa Ooishi , Shigeki Tomishima , Hiroki Shimano
IPC分类号： G11C11/407 , G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C7/00 , G11C8/00
CPC分类号： G11C29/808 , G11C29/842
摘要： A redundant memory cell column region provided corresponding to respective regular memory cell column regions can have data read and written through a sub I/O line pair and a main I/O line pair independent to those of the regular memory cell column region. Also, one redundant memory cell column region can be connected to a corresponding global I/O line pair G-I/O of any of the regular memory cell column regions via a multiplexer to be replaceable of any of two regular memory cell column regions.
摘要翻译：与相应的常规存储单元列区相对应地提供的冗余存储单元列区域可以通过与常规存储单元列区域独立的子I / O线对和主I / O线对读取和写入数据。此外，一个冗余存储单元列区域可以经由多路复用器连接到任何常规存储器单元列区域的对应全局I / O线对G-I / O，以可替换两个常规存储器单元列区域中的任一个。

30. 发明申请

US20130088279A1 Power Converter 审中-公开
标题翻译：电源转换器
公开(公告)号：US20130088279A1
公开(公告)日：2013-04-11
申请号：US13638372
申请日：2011-04-01
申请人： Hiroki Shimano , Yasuo Noto , Koichi Yahata , Seiji Funaba , Yoshio Akaishi
发明人： Hiroki Shimano , Yasuo Noto , Koichi Yahata , Seiji Funaba , Yoshio Akaishi
IPC分类号： H03K17/284
CPC分类号： H03K17/284 , H02M1/08 , H03K17/163 , H03K2217/0036
摘要： The present invention provides a power converter including a power semiconductor device, a driver circuit section that outputs a driving signal for driving the power semiconductor device, a buffer circuit section that includes a PNP transistor and an NPN transistor and that outputs a gate voltage for driving the power semiconductor device, a first delay circuit section that receives the driving signal and that generates a first delay signal on the basis of the received driving signal, a first MOSFET that has a drain electrode connected with the output of the buffer circuit section and that is driven on the basis of the first delay signal. A current flows through the buffer circuit section and the first MOSFET on the basis of the received driving signal, the first delay circuit section outputs the first delay signal after the buffer circuit section exits the transient state and turns on, and the gate voltage is applied to the power semiconductor device from the buffer circuit section to turn the power semiconductor device on by the switching operation of the first MOSFET based on the first delay signal.
摘要翻译：本发明提供了一种功率转换器，包括功率半导体器件，输出用于驱动功率半导体器件的驱动信号的驱动器电路部分，包括PNP晶体管和NPN晶体管的缓冲电路部分，并且输出用于驱动的栅极电压所述功率半导体器件，接收所述驱动信号并基于所接收的驱动信号产生第一延迟信号的第一延迟电路部，具有与所述缓冲电路部的输出连接的漏电极的第一MOSFET，以及与所述缓冲电路部的输出连接的第一MOSFET，基于第一延迟信号被驱动。 A电流根据接收到的驱动信号流过缓冲电路部分和第一MOSFET，第一延迟电路部分在缓冲电路部分退出瞬态之后输出第一延迟信号并导通，施加栅极电压从缓冲电路部分到功率半导体器件，通过基于第一延迟信号的第一MOSFET的开关操作使功率半导体器件导通。

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