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21. 发明申请

WO2018048562A1 TECHNOLOGIES FOR TRANSACTIONAL SYNCHRONIZATION OF DISTRIBUTED OBJECTS IN A FABRIC ARCHITECTURE 审中-公开
标题翻译：分布式对象在织物结构中的事务同步技术
公开(公告)号：WO2018048562A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/046107
申请日：2017-08-09
申请人： INTEL CORPORATION
发明人： BERNAT, Francesc Guim , DOSHI, Kshitij A. , RIVAS BARRAGAN, Daniel
IPC分类号： G06F13/38 , G06F9/46
CPC分类号： H04L49/103 , G06F3/067 , G06F12/084 , H04L29/08135 , H04L49/355 , H04L67/1097
摘要： Technologies for performing switch-based collective operations in a fabric architecture include a computing node that includes a host fabric interface (HFI) usable to communicate with network computing devices of the fabric architecture. The HFI is configured to associate an object with a transaction identifier generated by the HFI for a corresponding transactional synchronization session managed by the HFI of the computing node. Additionally, the HFI is configured to store received data associated with received write transaction that include the transaction identifier in a local buffer of the HFI. Upon receiving a transactional synchronization session termination request, the HFI is configured to initiate a write of the data stored in the local buffer of the HFI to one of the one or more data storage devices of the computing node. Other embodiments are described herein.
摘要翻译：用于在结构体系结构中执行基于交换机的集体操作的技术包括计算节点，该计算节点包括可用于与该结构体系结构的网络计算设备进行通信的主机结构接口（HFI）。 HFI被配置为将对象与由HFI生成的交易标识符相关联以用于由计算节点的HFI管理的对应交易同步会话。另外，HFI被配置为将接收的与包括事务标识符的写事务相关联的数据存储在HFI的本地缓冲区中。在接收到事务性同步会话终止请求时，HFI被配置为发起将存储在HFI的本地缓冲器中的数据写入到计算节点的一个或多个数据存储设备中的一个。这里描述了其他实施例。

22. 发明申请

WO2018005095A1 APPARATUSES, METHODS, AND SYSTEMS FOR GRANULAR AND ADAPTIVE HARDWARE TRANSACTIONAL SYNCHRONIZATION 审中-公开
标题翻译：颗粒状和自适应硬件交换同步的装置，方法和系统
公开(公告)号：WO2018005095A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/037455
申请日：2017-06-14
申请人： INTEL CORPORATION
发明人： DOSHI, Kshitij A. , HUGHES, Christopher J.
IPC分类号： G06F9/46
CPC分类号： G06F9/467 , G06F3/061 , G06F3/0637 , G06F3/0673
摘要： Methods and apparatuses relating to hardware transactions are described. In one embodiment, a processor includes one or more cores to concurrently execute a plurality of transactions, and a hardware transactional circuit to detect an occurrence of a software selected precursor in any of the plurality of transactions and abort at least one of the plurality of transactions on the occurrence unless an interface to software indicates the occurrence is to not cause an abort, wherein the occurrence is not a memory access of shared data by the plurality of transactions.
摘要翻译：描述与硬件交易有关的方法和设备。在一个实施例中，处理器包括一个或多个内核以同时执行多个事务，以及硬件事务处理电路，用于检测多个事务中的任一个中的软件选择前驱的发生，并中止多个事务中的至少一个除非与软件的接口指示事件不会导致中止，其中事件不是多次事务对共享数据的存储器访问。

23. 发明申请

WO2017117317A1 SYSTEMS, METHODS, AND APPARATUSES FOR FAULT TOLERANCE AND DETECTION 审中-公开
标题翻译：用于容错和检测的系统，方法和装置
公开(公告)号：WO2017117317A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/069062
申请日：2016-12-29
申请人： INTEL CORPORATION
发明人： OULD-AHMED-VALL, Elmoustapha , SAIR, Suleyman , DOSHI, Kshitij A. , YOUNT, Charles R.
IPC分类号： G06F11/18 , G06F15/80
CPC分类号： G06F11/079 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/3016 , G06F11/0745 , G06F11/0751 , G06F11/0772
摘要： Systems, methods, and apparatuses for fault tolerance and detection are described. For example, an apparatus including circuitry to replicate input sources of an instruction; arithmetic logic unit (ALU) circuitry to execute the instruction with replicated input sources using single instruction, multiple data (SIMD) hardware to produce a packed data result; and comparison circuitry coupled to the ALU circuitry to evaluate the packed data result and output a singular data result into a destination of the instruction is described.
摘要翻译：描述了用于容错和检测的系统，方法和装置。例如，一种包括复制指令的输入源的电路的设备; 算术逻辑单元（ALU）电路，用于使用单指令多数据（SIMD）硬件执行具有复制输入源的指令以产生打包数据结果; 以及耦合到ALU电路以评估打包数据结果并将奇异数据结果输出到指令的目的地的比较电路被描述。

24. 发明申请

WO2018004859A3 FABRIC ENCAPSULATED RESILIENT STORAGE 审中-公开
公开(公告)号：WO2018004859A3
公开(公告)日：2018-01-04
申请号：PCT/US2017/033108
申请日：2017-05-17
申请人： INTEL CORPORATION
发明人： GUIM BERNAT, Francesc , RIVAS BARRAGAN, Daniel , DOSHI, Kshitij A. , SCHMISSEUR, Mark A. , LARSEN, Steen
IPC分类号： G06F17/30
摘要： Fabric encapsulated resilient storage is hardware-assisted resilient storage in which the reliability capabilities of a storage server are abstracted and managed transparently by a host fabric interface (HFI) to a switch. The switch abstracts the reliability capabilities of a storage server into a level of resilience in a hierarchy of levels of resilience. The resilience levels are accessible by clients as a quantifiable characteristic of the storage server. The resilience levels are used by the switch fabric to filter which storage servers store objects responsive to client requests to store objects at a specified level of resilience.

25. 发明申请

WO2017172234A1 TECHNOLOGIES FOR MANAGING IMMUTABLE DATA ON A DATA STORAGE DEVICE 审中-公开
标题翻译：在数据存储设备上管理不可变数据的技术
公开(公告)号：WO2017172234A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/020395
申请日：2017-03-02
申请人： INTEL CORPORATION
发明人： TRIKA, Sanjeev N. , DOSHI, Kshitij A.
IPC分类号： G06F3/06
摘要： Technologies for managing immutable data include a data storage device having a data storage controller and memory for storing data. The data storage controller may receive requests from a host of the data storage device to mark data stored in the memory as immutable. In response to the request, the data storage controller is configured to set an immutable flag associated with the identified data to mark the identified data as immutable. The immutable flag, when set, provides an indication that the associated data is unmodifiable. In some embodiments, the data storage device may also compact and/or move the immutable data to an immutable memory region of the memory. Technologies to mark the immutable data as mutable, write to the immutable data, and delete or trim the immutable data are also disclosed.
摘要翻译：用于管理不可变数据的技术包括具有数据存储控制器和用于存储数据的存储器的数据存储设备。数据存储控制器可以接收来自数据存储设备的主机的请求，以将存储在存储器中的数据标记为不可变的。响应于该请求，数据存储控制器被配置为设置与所识别的数据相关联的不可变标志，以将所识别的数据标记为不可变的。不可变标志在设置时提供关联数据不可修改的指示。在一些实施例中，数据存储设备还可以将不可变数据压缩和/或移动到存储器的不可变存储区域。还公开了将不可变数据标记为可变数据，写入不可变数据以及删除或修剪不可变数据的技术。

26. 发明申请

WO2017112314A1 BYTE AND NIBBLE SORT INSTRUCTIONS 审中-公开
标题翻译： BYTE和NIBBLE排序说明
公开(公告)号：WO2017112314A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063655
申请日：2016-11-23
申请人： INTEL CORPORATION
发明人： MISHRA, Asit K. , DOSHI, Kshitij A. , OULD-AHMED-VALL, Elmoustapha , MARR, Deborah T.
IPC分类号： G06F9/30
CPC分类号： G06F9/3889 , G06F9/30 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30112 , G06F9/3861 , G06F9/3887
摘要： A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.
摘要翻译：处理器包括：第一寄存器，用于在第一寄存器内的多个位置处存储多个数据项;第二寄存器;以及执行单元，其可操作地耦合到第一寄存器和第二寄存器，所述执行单元包括实现分类指令的逻辑电路，所述分类指令用于按照数据项值的顺序对存储在所述第一寄存器中的所述多个数据项进行分类，并且在所述第二寄存器中存储多个索引，其中每个索引标识在分类之前与存储在第一寄存器中的数据项相关联的位置。

27. 发明申请

WO2017112195A1 PROCESSING DEVICES TO PERFORM A CONJUGATE PERMUTE INSTRUCTION 审中-公开
标题翻译：处理设备以执行共轭参考指令
公开(公告)号：WO2017112195A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062939
申请日：2016-11-18
申请人： INTEL CORPORATION
发明人： MISHRA, Asit K. , DOSHI, Kshitij A. , OULD-AHMED-VALL, Elmoustapha , CORBAL, Jesus , MARR, Deborah T.
IPC分类号： G06F15/80 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3887 , G06F9/30 , G06F9/30036 , G06F9/30098
摘要： Single Instruction, Multiple Data (SIMD) technologies are described. A processer may include a first register to receive a plurality of source elements and second register. The processor may receive a permute index at a third register. The conjugate permute index has elements, each of which corresponds to one of the source elements. The processor then stores each of the source elements to a position in the second register based on a select element corresponding to the source element.
摘要翻译：描述了单指令多数据（SIMD）技术。处理器可以包括用于接收多个源元素和第二寄存器的第一寄存器。处理器可以在第三寄存器处接收置换索引。共轭置换索引具有元素，每个元素对应于其中一个源元素。处理器然后基于对应于源元素的选择元素将每个源元素存储到第二寄存器中的位置。

28. 发明申请

WO2022139921A1 MANAGEMENT OF DISTRIBUTED SHARED MEMORY 审中-公开
公开(公告)号：WO2022139921A1
公开(公告)日：2022-06-30
申请号：PCT/US2021/051794
申请日：2021-09-23
申请人： INTEL CORPORATION
发明人： DOSHI, Kshitij A. , GUIM BERNAT, Francesc , PRABHAKARAN, Suraj , GOHAD, Tushar Sudhakar
IPC分类号： G06F12/1009 , G06F12/0813
摘要： Examples described herein relate to a network interface device. In some examples, the network interface device includes a device interface; input/output circuitry to receive Ethernet compliant packets and output Ethernet compliant packets; circuitry to monitor a particular page for a rate of data copying among nodes within a group of two or more nodes; and circuitry to perform one or more actions based, at least in part, on the rate of data copying among the nodes within the group of two or more nodes to attempt to reduce a number of copy operations of the data among the nodes within the group of two or more nodes, wherein the group of two or more nodes are part of a distributed shared memory (DSM).

29. 发明申请

WO2022072096A1 INFRASTRUCTURE PROCESSING UNIT 审中-公开
公开(公告)号：WO2022072096A1
公开(公告)日：2022-04-07
申请号：PCT/US2021/048092
申请日：2021-08-27
申请人： INTEL CORPORATION
发明人： VAN DE GROENENDAAL, Johan , DOSHI, Kshitij A. , CHEN, Edmund , SAHITA, Ravi , HERDRICH, Andrew J. , BERNSTEIN, Debra , SEVERNS-WILLIAMS, Christine E. , CUMMINGS, Uri V. , KAKAIYA, Utkarsh Y.
IPC分类号： G06F9/52 , H04L29/08 , G06F9/50 , H04L12/26 , G06F9/54
摘要： Examples described herein relate to an Infrastructure Processing Unit (IPU) that comprises: interface circuitry to provide a communicative coupling with a platform; network interface circuitry to provide a communicative coupling with a network medium; and circuitry to expose infrastructure services to be accessed by microservices for function composition.

30. 发明申请

WO2018111511A1 METHOD AND APPARATUS FOR MEMORY CONSISTENCY USING CACHE COHERENCY PROTOCOLS 审中-公开
公开(公告)号：WO2018111511A1
公开(公告)日：2018-06-21
申请号：PCT/US2017/062732
申请日：2017-11-21
申请人： INTEL CORPORATION
发明人： GUIM BURNAT, Francesc , DOSHI, Kshitij A. , BLANKENSHIP, Robert G.
IPC分类号： G06F12/0802
CPC分类号： G06F12/0884 , G06F12/0822 , G06F2212/6042
摘要： A request is received from a first node over a communication fabric, the request to acquire an access right of a cache line for accessing data stored in a memory location of a memory, the first node being one of a plurality of nodes sharing the memory. In response to the request, a second node is determined based on the cache line that has cached a copy of the data of the cache line in its local memory. A first message is transmitted to the second node over the communication fabric requesting the second node to invalidate the cache line. In response to a response received from the second node indicating that the cache line has been invalidated, a second message is transmitted to the first node over the communication fabric to grant the access right of the cache line to the first node.

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