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21. 发明申请

WO2018125463A1 FLIP-FLOP CIRCUIT WITH LOW-LEAKAGE TRANSISTORS 审中-公开
公开(公告)号：WO2018125463A1
公开(公告)日：2018-07-05
申请号：PCT/US2017/063448
申请日：2017-11-28
申请人： INTEL CORPORATION
发明人： AUGUSTINE, Charles , RIOS, Rafael , PAUL, Somnath , KHELLAH, Muhammad M.
IPC分类号： H03K3/037 , H03K3/356 , H03K3/012
摘要： Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

22. 发明申请

WO2018063165A1 NON-PLANAR GATE THIN FILM TRANSISTOR 审中-公开
标题翻译：非平面栅极薄膜晶体管
公开(公告)号：WO2018063165A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054014
申请日：2016-09-27
申请人： INTEL CORPORATION
发明人： SHARMA, Abhishek A. , LE, Van H. , DEWEY, Gilbert , RIOS, Rafael , KAVALIEROS, Jack T. , WANG, Yih , SHIVARAMAN, Shriram
IPC分类号： H01L21/768 , H01L29/786 , H01L23/50
CPC分类号： H01L29/78642 , H01L21/768 , H01L21/76802 , H01L23/50 , H01L29/66742 , H01L2224/16225 , H01L2924/15311
摘要： Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.
摘要翻译：本公开的实施例描述了非平面栅极薄膜晶体管。集成电路可以包括形成在衬底上的多个层，并且多个层可以包括源极或漏极中的第一个，形成在源极或漏极中的第一个上的层间电介质（ILD），以及在ILD上形成的源极或漏极中的第二个。半导体层可以形成在多个层的侧壁上。在半导体层上形成栅极介电层，并且栅极可以与栅极介电层接触。

23. 发明申请

WO2018004659A1 THREE TRANSISTOR MEMORY CELL WITH METAL OXIDE SEMICONDUCTORS AND SI TRANSISTORS 审中-公开
标题翻译：具有金属氧化物半导体和SI晶体管的三晶体管存储器单元
公开(公告)号：WO2018004659A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040715
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： LE, Van H. , DEWEY, Gilbert William , RIOS, Rafael , KAVALIEROS, Jack T. , RADOSAVLJEVIC, Marko , SHIVARAMAN, Shriram , METERELLIYOZ, Mesut
IPC分类号： H01L27/11 , H01L27/108 , G11C11/406
CPC分类号： H01L27/108 , G11C11/405 , G11C11/406 , H01L27/1225 , H01L29/7869
摘要： A three transistor memory cell is described with metal oxide semiconductors. The memory cell in some examples has a pass gate transistor having a source coupled to a read bit line and a gate coupled to a read word line, a sensing transistor having a source coupled to a drain of the pass gate transistor, a charging transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor, wherein the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a second metal layer coupled to the gate of the charging transistor.
摘要翻译：使用金属氧化物半导体来描述三晶体管存储器单元。存储器单元在一些示例中具有传输门晶体管，其具有耦合到读位线的源极和耦合到读字线的栅极，传感晶体管具有耦合到传输门晶体管的漏极的源极，具有在第一金属层中的源极和漏极以及在所述源极和所述漏极之间的栅极，其中所述栅极具有在所述源极和所述漏极之间并且耦合到所述源极和所述漏极的沟道，所述沟道由金属氧化物半导体形成，其中所述充电晶体管耦合到感测晶体管的栅极，并且第二金属层中的栅电极耦合到充电晶体管的栅极。

24. 发明申请

WO2017171824A1 HIGH MOBILITY ASYMMETRIC FIELD EFFECT TRANSISTORS WITH A BAND-OFFSET SEMICONDUCTOR DRAIN SPACER 审中-公开
标题翻译：带偏移量半导体漏间隔物的高迁移率不对称场效应晶体管
公开(公告)号：WO2017171824A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025441
申请日：2016-03-31
申请人： INTEL CORPORATION
发明人： HUANG, Cheng-Ying , RACHMADY, Willy , KAVALIEROS, Jack T. , METZ, Matthew V. , CHU-KUNG, Benjamin , DEWEY, Gilbert , RIOS, Rafael
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7786 , H01L29/0834 , H01L29/205 , H01L29/66356 , H01L29/66462 , H01L29/6656 , H01L29/7391 , H01L29/78 , H01L29/785
摘要： An embodiment includes a field effect transistor, comprising: a source region comprising a first III-V material doped to a first conductivity type; a drain region comprising a second III-V material doped to a second conductivity type that is opposite the first conductivity type; a gate electrode disposed over a channel region comprising a third III-V material; and a first spacer, between the channel and drain regions, comprising a fourth III-V material having a charge carrier-blocking band offset from the third III-V material. Other embodiments are described herein.
摘要翻译：一个实施例包括场效应晶体管，包括：源区，包括掺杂成第一导电类型的第一III-V族材料; 漏极区域，包括掺杂成与第一导电类型相反的第二导电类型的第二III-V族材料; 设置在包括第三III-V材料的沟道区上的栅电极; 以及位于沟道区和漏极区之间的第一间隔物，包括具有偏离第三III-V族材料的电荷载流子阻挡带的第四III-V族材料。这里描述了其他实施例。

25. 发明申请

WO2017171739A1 TRANSISTOR GATE-CHANNEL ARRANGEMENTS 审中-公开
标题翻译：晶体管栅极通道安排
公开(公告)号：WO2017171739A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/024828
申请日：2016-03-30
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert W. , RIOS, Rafael , SHIVARAMAN, Shriram , RADOSAVLJEVIC, Marko , MILLARD, Kent E. , FRENCH, Marc C. , LE, Van H.
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/408 , H01L29/0673 , H01L29/221 , H01L29/41791 , H01L29/42364 , H01L29/42376 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66795 , H01L29/66969 , H01L29/775 , H01L29/7782 , H01L29/7786 , H01L29/785 , H01L29/7869 , H01L29/78696 , H01L2029/7858
摘要： Disclosed herein are transistor gate-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material, a high-k dielectric disposed between the gate electrode material and the channel material, and indium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material.
摘要翻译：这里公开了晶体管栅极沟道布置以及相关的方法和器件。例如，在一些实施例中，晶体管栅极沟道排列可以包括沟道材料和晶体管栅极叠层。晶体管栅极叠层可以包括栅电极材料，设置在栅电极材料和沟道材料之间的高k电介质以及设置在高k电介质材料和沟道材料之间的铟镓锌氧化物（IGZO）。 p>

26. 发明申请

WO2017111798A8 HIGH RETENTION TIME MEMORY ELEMENT WITH DUAL GATE DEVICES 审中-公开
公开(公告)号：WO2017111798A8
公开(公告)日：2017-06-29
申请号：PCT/US2015/000322
申请日：2015-12-23
申请人： INTEL CORPORATION
发明人： RIOS, Rafael , DEWEY, Gilbert , LE, Van, H. , KAVALIEROS, Jack , METERELLIYOZ, Mesut
IPC分类号： G11C11/409 , G11C11/4097
摘要： A high retention time memory element is described that has dual gate devices. In one example, the memory element has a write transistor with a metal gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.

27. 发明申请

WO2005010994A1 NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION 审中-公开
标题翻译：非门式半导体器件，部分或完全包裹在门电极和制造方法
公开(公告)号：WO2005010994A1
公开(公告)日：2005-02-03
申请号：PCT/US2003/040320
申请日：2003-12-15
申请人： INTEL CORPORATION
发明人： HARELAND, Scott , CHAU, Robert , DOYLE, Brian , RIOS, Rafael , LINTON, Jr., Tom , DATTA, Suman
IPC分类号： H01L29/423
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66772 , H01L29/66795
摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译：描述了非平面半导体器件及其制造方法。非平面半导体器件包括半导体本体，其半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对侧壁上的栅电介质相邻并位于半导体本体底表面上的栅电介质之下的栅电介质上。在栅电极的相对侧上的半导体本体中形成一对源/漏区。

28. 发明申请

WO2018182689A1 VERTICAL SHARED GATE THIN-FILM TRANSISTOR-BASED CHARGE STORAGE MEMORY 审中-公开
公开(公告)号：WO2018182689A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025391
申请日：2017-03-31
申请人： INTEL CORPORATION
发明人： SHARMA, Abhishek Anil , LE, Van H. , DEWEY, Gilbert William , RIOS, Rafael , KAVALIEROS, Jack T. , WANG, Yih , SHIVARAMAN, Shriram
IPC分类号： H01L27/108 , H01L29/786 , H01L27/12
摘要： A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.

29. 发明申请

WO2018063347A1 SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING A HIGH MOBILITY LOW CONTACT RESISTANCE SEMICONDUCTING OXIDE IN METAL CONTACT VIAS FOR THIN FILM TRANSISTORS 审中-公开
标题翻译：用于实现薄膜晶体管中高迁移率低接触电阻半导体氧化物金属接触VIAS的系统，方法和设备
公开(公告)号：WO2018063347A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054847
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： DEWEY, Gilbert , LE, Van H. , RIOS, Rafael , KAVALIEROS, Jack T. , SHIVARAMAN, Shriram
IPC分类号： H01L29/10 , H01L29/49 , H01L29/786
摘要： In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors. For instance, there is disclosed in accordance with one embodiment an oxide semiconductor transistor, having therein: a substrate layer; a channel layer formed atop the substrate; a metal gate and a gate oxide material formed atop the semiconducting oxide material of the channel layer; spacers positioned adjacent to the gate and gate oxide material; a dielectric layer formed atop the channel layer, the dielectric layer encompassing the spacers, the gate, and the gate oxide material; contact vias opened into the dielectric material forming an opening through the dielectric layer to the channel layer; a high mobility liner material lining the contact vias and in direct contact with the channel layer, the high mobility liner formed from a high mobility oxide material; and metallic contact material filling the contact vias opened into the dielectric material and separated from the channel layer by the high mobility liner of the contact vias. Other related embodiments are disclosed.
摘要翻译：根据所公开的实施例，提供了用于在用于薄膜晶体管的金属接触过孔中实现高迁移率低接触电阻半导体氧化物的系统，方法和设备。例如，根据一个实施例公开了一种氧化物半导体晶体管，其中具有：衬底层; 在衬底上形成的沟道层; 金属栅极和在沟道层的半导体氧化物材料顶上形成的栅极氧化物材料; 位于栅极和栅极氧化物材料附近的间隔物; 在所述沟道层顶上形成的介电层，所述介电层包围所述间隔件，所述栅极和所述栅极氧化物材料; 在电介质材料中开口的接触通孔形成穿过电介质层到达沟道层的开口; 高迁移率衬里材料，衬于接触过孔并与沟道层直接接触，高迁移率衬里由高迁移率氧化物材料形成; 以及金属接触材料，其填充通向所述电介质材料的所述接触通孔并且通过所述接触通孔的所述高迁移率衬垫与所述沟道层分离。披露了其他相关的实施例。

30. 发明申请

WO2018004667A1 TWO TRANSISTOR MEMORY CELL USING HIGH MOBILITY METAL OXIDE SEMICONDUCTORS 审中-公开
标题翻译：两个晶体管存储器使用高迁移率金属氧化物半导体
公开(公告)号：WO2018004667A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040764
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： LE, Van H. , DEWEY, Gilbert William , RADOSAVLJEVIC, Marko , RIOS, Rafael , KAVALIEROS, Jack T. , SHIVARAMAN, Shriram , METERELLIYOZ, Mesut
IPC分类号： H01L27/11 , H01L27/115 , H01L27/108
CPC分类号： H01L27/108 , G11C11/403 , G11C11/405 , H01L27/1225 , H01L29/7869
摘要： A two transistor memory cell is described that uses high mobility amorphous oxide semiconductors. In one example, a sensing transistor has a source and a drain in a first metal layer and a gate between the source and the drain. The gate has a channel formed of a metal oxide semiconductor. A charging transistor has a source and a drain in a second metal layer and a gate channel also formed of metal oxide semiconductor, wherein the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a third metal layer is coupled to the gate of the charging transistor.
摘要翻译：描述了使用高迁移率无定形氧化物半导体的双晶体管存储器单元。在一个示例中，感测晶体管具有第一金属层中的源极和漏极以及源极和漏极之间的栅极。该栅极具有由金属氧化物半导体形成的沟道。充电晶体管具有在第二金属层中的源极和漏极以及也由金属氧化物半导体形成的栅极沟道，其中充电晶体管的源极耦合到感测晶体管的栅极，并且栅极电极位于第三金属层耦合到充电晶体管的栅极。

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