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21. 发明申请

US20100248442A1 METHODS OF FORMING A PHASE CHANGE MEMORY DEVICE 有权
标题翻译：形成相变存储器件的方法
公开(公告)号：US20100248442A1
公开(公告)日：2010-09-30
申请号：US12731637
申请日：2010-03-25
申请人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Young-Lim Park , Jung-Hyeon Kim
发明人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Young-Lim Park , Jung-Hyeon Kim
IPC分类号： H01L21/02
CPC分类号： H01L45/1616 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.
摘要翻译：提供形成相变存储器件的方法。可以制备具有下电极和层间绝缘层的半导体器件。下电极可以被层间绝缘层包围。可以将源气体，反应气体和吹扫气体注入到半导体制造装置的处理室中，以在半导体衬底上形成相变材料层。源气体可以同时注入到处理室中。相变材料层可以通过层间绝缘层与下电极接触。可以蚀刻相变材料层以在层间绝缘层中形成相变存储单元。可以在相变存储单元上形成上电极。

22. 发明授权

US07778008B2 Capacitor structure and method of manufacturing the same 失效
标题翻译：电容器结构及其制造方法
公开(公告)号：US07778008B2
公开(公告)日：2010-08-17
申请号：US11983991
申请日：2007-11-13
申请人： Keun-Bong Lee , Jung-Hyeon Kim
发明人： Keun-Bong Lee , Jung-Hyeon Kim
IPC分类号： H01G4/005 , H01G4/06
CPC分类号： H01G4/005 , H01G4/012 , H01G4/30 , Y10T29/435
摘要： In a capacitor structure and a method of manufacturing the capacitor structure, first and second conductive patterns are formed on a substrate. The first and second conductive patterns extend in a first direction. The first and second conductive patterns are alternately arranged to be spaced apart from one another in a second direction substantially perpendicular to the first direction. An insulating interlayer is formed on the substrate to cover the first and second conductive patterns. Third and fourth conductive patterns extending in a third direction lying at an angle of between about 0° and about 90° relative to the first direction are formed on the insulating interlayer. The third and fourth conductive patterns are alternately arranged to be spaced apart from one another in a fourth direction substantially perpendicular to the third direction.
摘要翻译：在电容器结构和制造电容器结构的方法中，在基板上形成第一和第二导电图案。第一和第二导电图案沿第一方向延伸。第一和第二导电图案交替地布置成在基本上垂直于第一方向的第二方向上彼此间隔开。在衬底上形成绝缘中间层以覆盖第一和第二导电图案。在绝缘中间层上形成有相对于第一方向以约0°至约90°之间的角度在第三方向延伸的第三和第四导电图案。第三和第四导电图案交替地布置成在基本上垂直于第三方向的第四方向上彼此间隔开。

23. 发明授权

US07656180B2 Burn-in board connection device and method 有权
标题翻译：老化板连接装置及方法
公开(公告)号：US07656180B2
公开(公告)日：2010-02-02
申请号：US11937342
申请日：2007-11-08
申请人： Jae-Nam Lee , Jung-Hyeon Kim , Ju-II Kang , Jin-Woo Yang
发明人： Jae-Nam Lee , Jung-Hyeon Kim , Ju-II Kang , Jin-Woo Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2817 , G01R31/2863
摘要： A burn-in board connection device includes a first connection unit to hold a burn-in board and move in a first direction perpendicular to the burn-in board that is inserted in a chamber of a burn-in test device, a second connection unit to move in a second direction parallel to the burn-in board to attach/detach the burn-in board that is held by the first connection unit to/from a connector disposed in the chamber. A burn-in board connection method includes coupling a finger to the burn-in board by moving the finger in a first direction, attaching the burn-in board to a connector by moving the finger in a second direction, and driving the finger by converting a rotation of a servo motor into a linear movement of the finger.
摘要翻译：老化板连接装置包括：第一连接单元，用于保持老化板并且沿垂直于插入老化测试装置的室中的老化板的第一方向移动;第二连接单元沿平行于老化板的第二方向移动以将由第一连接单元保持的老化板与设置在腔室中的连接器相连接/分离。老化板连接方法包括通过沿第一方向移动手指将手指连接到老化板，通过沿第二方向移动手指将老化板附接到连接器，并且通过转换来驱动手指伺服电动机旋转到手指的线性运动。

24. 发明申请

US20090189152A1 FERROELECTRIC MEMORY DEVICE 审中-公开
标题翻译：电磁存储器件
公开(公告)号：US20090189152A1
公开(公告)日：2009-07-30
申请号：US12354990
申请日：2009-01-16
申请人： Byeong-Ok Cho , Moon-Sook Lee , Man-Hyoung Ryoo , Jung-Hyeon Kim , Takahiro Yasue
发明人： Byeong-Ok Cho , Moon-Sook Lee , Man-Hyoung Ryoo , Jung-Hyeon Kim , Takahiro Yasue
IPC分类号： H01L51/00 , H01L29/76
CPC分类号： H01L29/78391 , B82Y10/00 , G11C11/22 , H01L29/40111 , H01L29/516 , H01L29/6684
摘要： Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode.
摘要翻译：提供了一种铁电存储器件。铁电存储器件包括在衬底上的无机沟道图案，在衬底上彼此间隔开的源电极和漏电极，并与无机沟道图案接触，邻近无机沟道图案设置的栅电极和有机铁电体介于无机通道图案和栅电极之间的层。

25. 发明申请

US20080164901A1 Multilayer type test board assembly for high-precision inspection 有权
标题翻译：多层型测试板组件进行高精度检测
公开(公告)号：US20080164901A1
公开(公告)日：2008-07-10
申请号：US12006543
申请日：2008-01-03
申请人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
发明人： Min-Gu Kim , Young-Soo An , Ho-Jeong Choi , Jung-Hyeon Kim
IPC分类号： G01R1/02
CPC分类号： G01R31/2851 , G01R1/04 , H05K1/144 , H05K1/148 , H05K2201/042 , H05K2201/09972 , H05K2201/10371
摘要： There is provided a multilayer type test board assembly for high-precision inspection. The multilayer test board assembly comprises: a plurality of test boards separated from each other according to their functions, having input/output signal terminals, and including at least one test board each having a first section where first mounting devices sensitive to an influence of electrical signals are mounted and a second section where second mounting devices insensitive to an influence of electrical signals are mounted; spacers that arrange the test boards in parallel by spacing apart the test boards by predetermined intervals; connection cables connected to the input/output signal terminals of the test boards; and a signal shielding fence formed on each of the at least one test board so as to protect the first mounting devices from electrical signals generated by the second mounting devices.
摘要翻译：提供了一种用于高精度检测的多层型测试板组件。多层测试板组件包括：根据功能彼此分离的多个测试板，具有输入/输出信号端子，并且包括至少一个测试板，每个测试板具有第一部分，其中第一安装器件对电气的影响敏感信号被安装，并且第二部分安装对电信号的影响不敏感的第二安装装置; 间隔件通过以预定的间隔隔开测试板来平行布置测试板; 连接电缆连接到测试板的输入/输出信号端子; 以及形成在所述至少一个测试板中的每一个上的信号屏蔽栅栏，以便保护所述第一安装装置免受由所述第二安装装置产生的电信号。

26. 发明申请

US20080123245A1 Capacitor structure 失效
标题翻译：电容结构
公开(公告)号：US20080123245A1
公开(公告)日：2008-05-29
申请号：US11998132
申请日：2007-11-28
申请人： Keun-Bong Lee , Jung-Hyeon Kim
发明人： Keun-Bong Lee , Jung-Hyeon Kim
IPC分类号： H01G4/012
CPC分类号： H01G4/012 , H01G4/005 , H01G4/236 , H01G4/30
摘要： A capacitor structure includes an insulating layer, first conductive patterns, second conductive patterns, an insulating interlayer, third conductive patterns, and fourth conductive patterns. The first and second conductive patterns are alternately arranged on the insulating layer to be spaced apart from one another. The first and second conductive patterns have side faces where concave portions and convex portions are formed. The insulating interlayer is formed on the insulating layer to cover the first and second conductive patterns. The third and fourth conductive patterns are alternately arranged on the insulating interlayer to be spaced apart from one another. The third and fourth conductive patterns have side faces where concave portions and convex portions are formed.
摘要翻译：电容器结构包括绝缘层，第一导电图案，第二导电图案，绝缘夹层，第三导电图案和第四导电图案。第一和第二导电图案交替地布置在绝缘层上以彼此间隔开。第一和第二导电图案具有形成凹部和凸部的侧面。在绝缘层上形成绝缘中间层以覆盖第一和第二导电图案。第三和第四导电图案交替地布置在绝缘中间层上以彼此间隔开。第三和第四导电图案具有形成凹部和凸部的侧面。

27. 发明授权

US08222644B2 Fan-out unit and thin-film transistor array substrate having the same 有权
标题翻译：扇出单元和薄膜晶体管阵列基板
公开(公告)号：US08222644B2
公开(公告)日：2012-07-17
申请号：US12637658
申请日：2009-12-14
申请人： Sung-Hoon Yang , So-Woon Kim , Yeon-Ju Kim , So-Hyun Lee , Kwang-Hoon Lee , Mun-Soo Park , Jung-Hyeon Kim
发明人： Sung-Hoon Yang , So-Woon Kim , Yeon-Ju Kim , So-Hyun Lee , Kwang-Hoon Lee , Mun-Soo Park , Jung-Hyeon Kim
IPC分类号： H01L29/15 , G02F1/1345
CPC分类号： G02F1/1345 , H01L27/124 , H05K1/0265 , H05K1/167 , H05K2201/0784 , H05K2201/09263
摘要： A fan-out unit which can control a resistance difference among channels with efficient space utilization and a thin-film transistor (TFT) array substrate having the fan-out unit are presented. The fan-out unit includes: an insulating substrate; a first wiring layer which is formed on the insulating substrate and connected to a pad; a second wiring layer which is formed on the insulating substrate and connected to a TFT; and a resistance controller which is connected between the first wiring layer and the second wiring layer and includes a plurality of first resistors extending parallel to the first wiring layer and a plurality of second resistors extending perpendicular to the first resistors and alternately connecting to the first resistors, wherein the first resistors are longer than the second resistors.
摘要翻译：提出了一种能够控制具有高效空间利用的通道之间的电阻差的扇出单元和具有扇出单元的薄膜晶体管（TFT）阵列基板。扇出单元包括：绝缘基板; 第一布线层，其形成在所述绝缘基板上并连接到焊盘; 第二布线层，其形成在绝缘基板上并连接到TFT; 以及电阻控制器，其连接在第一布线层和第二布线层之间，并且包括平行于第一布线层延伸的多个第一电阻器和垂直于第一电阻器延伸的多个第二电阻器，并交替地连接到第一电阻器，其中所述第一电阻器比所述第二电阻器长。

28. 发明授权

US08114203B2 Units for collecting particles, apparatus including the same and methods for collecting particles using the same 有权
标题翻译：用于收集颗粒的单元，包括该颗粒的装置以及使用该颗粒收集颗粒的方法
公开(公告)号：US08114203B2
公开(公告)日：2012-02-14
申请号：US12009817
申请日：2008-01-22
申请人： Ki-Su Kim , Jung-Hyeon Kim
发明人： Ki-Su Kim , Jung-Hyeon Kim
IPC分类号： B01D51/08
CPC分类号： C23C16/4412 , B01D45/02 , B01D45/04 , H01L21/67103
摘要： A collection unit includes an exhaust conduit providing a path through which a process gas flows, a trap installed in the exhaust conduit, and a collection line connected to the trap. The trap has an inlet through which particles in the process are introduced into the trap, and the collection line penetrates a portion of the exhaust conduit to extend toward an outside region of the exhaust conduit. An apparatus including the collection unit and a method for collecting particles using the same are also provided.
摘要翻译：收集单元包括排气管道，其提供工艺气体通过的路径，安装在排气管道中的捕集器和连接到捕集器的收集管线。捕集器具有入口，通过该入口将过程中的颗粒引入到捕集器中，并且收集管线穿过排气管道的一部分以朝向排气管道的外部区域延伸。还提供了一种包括收集单元的装置和使用其的收集颗粒的方法。

29. 发明申请

US20100164101A1 Ball land structure having barrier pattern 审中-公开
标题翻译：具有障碍图案的球场结构
公开(公告)号：US20100164101A1
公开(公告)日：2010-07-01
申请号：US12654477
申请日：2009-12-22
申请人： Wang-Jae Lee , Yong-Jin Jung , Jung-Hyeon Kim
发明人： Wang-Jae Lee , Yong-Jin Jung , Jung-Hyeon Kim
IPC分类号： H01L23/498 , H01R12/04
CPC分类号： H01L23/13 , H01L23/49811 , H01L24/48 , H01L24/97 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01047 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K1/111 , H05K3/3452 , H05K2201/0969 , H05K2201/09781 , H05K2201/0989 , H05K2201/099 , Y02P70/611 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Disclosed is a ball land structure suitable for use with a semiconductor package. The ball land structure includes a ball land and a barrier on a core. The barrier may be configured to connect to the ball land so as to form a barrier hole between an edge of the ball land and an edge of the barrier thus exposing a portion of the core. A solder mask may be deposited on the ball land and a portion of the core exposed by the barrier hole so as to partially expose the core.
摘要翻译：公开了适用于半导体封装的球面结构。球场结构包括球场和核心上的障碍物。阻挡层可以被构造成连接到球区，以便在球台的边缘和屏障的边缘之间形成阻挡孔，从而暴露出核心的一部分。焊盘可以沉积在球台上，并且芯的一部分由阻挡孔暴露以部分地露出芯。

30. 发明申请

US20100127731A1 Antifuse circuit of inverter type and method of programming the same 审中-公开
标题翻译：逆变器类型的防腐电路及其编程方法
公开(公告)号：US20100127731A1
公开(公告)日：2010-05-27
申请号：US12585276
申请日：2009-09-10
申请人： Jae-Yong Seo , Gu-Gwan Kang , Tae-Hun Kang , Hong-Sik Park , Jung-Hyeon Kim
发明人： Jae-Yong Seo , Gu-Gwan Kang , Tae-Hun Kang , Hong-Sik Park , Jung-Hyeon Kim
IPC分类号： H03K19/173 , H01H37/76
CPC分类号： H03K19/173 , G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments are directed to an antifuse circuit of an inverter type and a method of programming the same. The antifuse circuit has improved corrosion resistance, utilizes lesser chip area and can be programmed at a low voltage. The antifuse circuit includes a PMOS transistor with the gate coupled to a drive power voltage terminal and the source coupled to an anti-pad terminal. During programming the PMOS transistor is off and the source receives an alternating current. Programming the antifuse circuit involves trapping a plurality of electron in an STI region as a result of gate-induced drain leakage. The antifuse circuit also includes an NMOS transistor with the drain connected to the drain of the PMOS transistor, the source connected to ground and the gate connected to a program control signal. The antifuse circuit results in reliable fuse programming at a low voltage by using the PMOS transistor as an anti-fuse device.
摘要翻译：示例性实施例涉及逆变器类型的反熔丝电路及其编程方法。反熔丝电路具有改善的耐腐蚀性，使用较小的芯片面积，并且可以在低电压下编程。反熔丝电路包括PMOS晶体管，其栅极耦合到驱动电源电压端子，并且源极耦合到反焊盘端子。在编程期间，PMOS晶体管截止，源极接收交流电流。对反熔丝电路的编程涉及在栅极引起的漏极泄漏的情况下在STI区域中捕获多个电子。反熔丝电路还包括NMOS晶体管，漏极连接到PMOS晶体管的漏极，源极连接到地，栅极连接到编程控制信号。反熔丝电路通过使用PMOS晶体管作为反熔丝器件，在低电压下实现可靠的熔丝编程。

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