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    • 24. 发明申请
    • TRANSACTION FLOW CONTROL IN PCI EXPRESS FABRIC
    • PCI EXPRESS FABRIC的交易流量控制
    • US20090037616A1
    • 2009-02-05
    • US11831861
    • 2007-07-31
    • Paul V. BrownellDavid L. Matthews
    • Paul V. BrownellDavid L. Matthews
    • G06F3/00
    • G06F13/4221
    • A computer-executed method for controlling transaction flow in a network comprises communicating transaction packets among a plurality of devices in a network fabric and subdividing a memory into a plurality of memory segments for storing received transaction cycles according to transaction packet type comprising posted, non-posted, and completion cycles. A plurality of transaction cycles are received in the memory segment plurality at a target device and transaction cycle priority is allocated according to transaction packet type wherein posted cycles have highest priority. Cycles are retrieved from the memory segment plurality in an order determined by priority.
    • 用于控制网络中的事务流的计算机执行方法包括在网络结构中的多个设备之间传送交易分组,并将存储器细分为多个存储器段,用于根据事务分组类型存储所接收的事务周期, 发布和完成周期。 在目标设备处的多个存储器段中接收多个事务周期,并且根据事务分组类型来分配事务周期优先级,其中发布周期具有最高优先级。 按照由优先级确定的顺序从多个存储器段检索循环。
    • 25. 发明授权
    • System and method for adaptively adjusting clock skew in a variably loaded memory bus
    • 用于在可变加载的存储器总线中自适应地调整时钟偏移的系统和方法
    • US06915443B2
    • 2005-07-05
    • US09904814
    • 2001-07-13
    • Christopher D. McBridePaul V. BrownellTimothy R. McJunkin
    • Christopher D. McBridePaul V. BrownellTimothy R. McJunkin
    • G06F1/10G06F1/04G06F1/12G06F13/00G11C7/00
    • G06F1/10
    • The preferred embodiments of the present invention are directed to the selective phase lag and time delay of clock signals within a computer system to compensate for additional parasitic capacitance that may be added to that system because of its open architecture. More particularly, the preferred embodiments are directed to clock signal path circuits where each circuit has multiple signal paths of varying lengths. By allowing the clock signals to propagate along a particular path, phase lag or time delay is added to those clock signals. Selection of a particular path for the clock signal is made by activating electrically controlled switches which themselves are activated or deactivated by software programs that run during power-up of the computer system that determine required phase lag or time delay of those clock signals as a function of parasitic capacitance in the computer system.
    • 本发明的优选实施例涉及计算机系统内的时钟信号的选择性相位滞后和时间延迟,以补偿由于其开放架构而可能添加到该系统的附加寄生电容。 更具体地,优选实施例涉及时钟信号路径电路,其中每个电路具有不同长度的多个信号路径。 通过允许时钟信号沿特定路径传播,相位滞后或时间延迟被添加到那些时钟信号。 用于时钟信号的特定路径的选择是通过激活电控开关来实现的,该开关本身由计算机系统的上电期间运行的软件程序激活或去激活,所述软件程序确定那些时钟信号作为一个功能的所需相位滞后或时间延迟 的计算机系统中的寄生电容。