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    • 25. 发明授权
    • System and method for EEPROM architecture
    • EEPROM架构的系统和方法
    • US08470669B2
    • 2013-06-25
    • US12959229
    • 2010-12-02
    • Yipeng JanZhen YangShenghe Huang
    • Yipeng JanZhen YangShenghe Huang
    • H01L21/00
    • H01L21/28273H01L21/26586H01L27/11521H01L27/11524H01L29/42324H01L29/66825H01L29/7881
    • A method for manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) device includes providing a substrate and forming a gate oxide over the substrate. Also, the method includes providing a mask overlying the gate oxide layer, the mask defining a tunnel opening. The method additionally includes performing selective etching over the mask to form a tunnel oxide layer. The method includes forming a floating gate over the tunnel oxide layer and a selective gate over the gate oxide layer. The method includes angle doping a region of the substrate using the floating gate as a mask to obtain a first doped region. The method further includes forming a dielectric layer over the floating gate and a control gate over the dielectric layer. The method additionally includes angle doping a second region of the substrate using the selective gate as a mask to obtain a second doped region, wherein the first and second doped regions partially overlap.
    • 一种用于制造电可擦除可编程只读存储器(EEPROM)器件的方法包括提供衬底并在衬底上形成栅极氧化物。 此外,该方法包括提供覆盖栅极氧化物层的掩模,掩模限定隧道开口。 该方法另外包括在掩模上执行选择性蚀刻以形成隧道氧化物层。 该方法包括在隧道氧化物层上形成浮置栅极,在栅极氧化物层上形成选择栅极。 该方法包括使用浮置栅极作为掩模对衬底的区域进行角度掺杂以获得第一掺杂区域。 所述方法还包括在所述浮动栅极上形成介电层和在所述电介质层上形成控制栅极。 该方法另外包括使用选择栅极作为掩模的角度掺杂衬底的第二区域以获得第二掺杂区域,其中第一和第二掺杂区域部分重叠。
    • 29. 发明申请
    • CAPLESS LOW DROP-OUT VOLTAGE REGULATOR WITH FAST OVERVOLTAGE RESPONSE
    • 具有快速过压响应的无漏电低压稳压器
    • US20100277148A1
    • 2010-11-04
    • US12679485
    • 2008-09-29
    • Hui ZhaoZhen Yang
    • Hui ZhaoZhen Yang
    • G05F1/10
    • G05F1/571
    • A voltage regulator is provided having one or more discharger circuits that compensate for low on-chip output capacitance and a slow loop response time. In one embodiment, the voltage regulator includes an output transistor coupled to an output voltage line, an output voltage sensing arrangement coupled to the output voltage line for producing an output feedback voltage, and an error amplifier coupled to the output feedback voltage, the output transistor, and a reference voltage for applying feedback control to the output transistor. A first discharger circuit is coupled to the output voltage line and to a reference potential, the first discharger circuit being triggered by a steep-rise overvoltage condition. In another embodiment, a combination of fast and slow discharger circuits is used to improve the load step response—i.e., to stop the output voltage from jumping too high and to pull it back to stable value very quickly, such that the load circuits are protected.
    • 提供了具有一个或多个放大器电路的电压调节器,其补偿片上输出电容的低电平和缓慢的环路响应时间。 在一个实施例中,电压调节器包括耦合到输出电压线的输出晶体管,耦合到输出电压线的输出电压感测装置,用于产生输出反馈电压,以及耦合到输出反馈电压的误差放大器,输出晶体管 以及用于向输出晶体管施加反馈控制的参考电压。 第一放电电路耦合到输出电压线和参考电位,第一放电电路由陡升过压状态触发。 在另一个实施例中,使用快速和慢速放电器电路的组合来改善负载阶跃响应 - 即停止输出电压跳跃太高并将其非常快地拉回稳定值,使得负载电路被保护 。