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    • 22. 发明申请
    • Memory testing apparatus and method
    • 记忆体检测装置及方法
    • US20050043912A1
    • 2005-02-24
    • US10851151
    • 2004-05-24
    • Ki-Sang KangTsutomu AkiyamaJe-Young Park
    • Ki-Sang KangTsutomu AkiyamaJe-Young Park
    • G01R31/3183G01R31/28G11C29/00G11C29/56H01L21/66G06F19/00
    • G11C29/56004G11C29/56G11C2029/1208
    • Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During funtional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.
    • 提供了一种操作这样的装置的存储器件测试装置和方法,其可以减少测试诸如DRAM的存储器件所需的时间。 存储器测试装置包括模式发生器,测试头,地址指针,选择器,故障存储器,故障位计数器和用于协调各种元件的操作的控制器。 根据从控制器接收到的信号,模式发生器将产生背景模式或测试模式和地址信息,这些模式和地址信息又被输出到被测存储器件和选择器。 在对存储器件进行功能测试期间,故障数据被累积在故障存储器中,并且随后当将背景或测试模式写入存储器件时,使用来自地址指针的地址信息将其输出到故障位计数器。
    • 25. 发明授权
    • Test apparatus and cable guide unit
    • 测试设备和电缆引导单元
    • US07349617B2
    • 2008-03-25
    • US11827280
    • 2007-07-11
    • Masashi ShibataToshiyuki OkayasuTsutomu Akiyama
    • Masashi ShibataToshiyuki OkayasuTsutomu Akiyama
    • G02B6/00
    • G01R31/31905
    • A test apparatus includes a test head including a plurality of test boards for applying a test pattern to a device under test, a main frame for controlling a test sequence by the test head, and a fiber optic cable unit including a plurality of flat cables for optically coupling the test head and the main frame, a plurality of fiber optic cables, a dam for coupling the fiber optic cable unit and the plurality of fiber optic cables, a circumferential difference absorption apparatus for absorbing the difference in circumferential length between the plurality of flat cables of the fiber optic cable unit, and a cable guide unit for bending and holding the fiber optic cables coupled to the test board of the main frame.
    • 测试装置包括测试头,该测试头包括用于将测试图案施加到被测设备的多个测试板,用于由测试头控制测试序列的主框架,以及包括多个扁平电缆的光缆单元, 光学耦合测试头和主框架,多根光纤电缆,用于耦合光纤电缆单元和多根光纤电缆的隔离件,用于吸收多个光纤电缆单元之间的周长差的周向差分吸收设备 光纤电缆单元的扁平电缆,以及用于弯曲和保持耦合到主框架的测试板的光纤电缆的电缆引导单元。
    • 26. 发明授权
    • Test apparatus and cable guide unit
    • 测试设备和电缆引导单元
    • US07286742B2
    • 2007-10-23
    • US11415372
    • 2006-05-01
    • Masashi ShibataToshiyuki OkayasuTsutomu Akiyama
    • Masashi ShibataToshiyuki OkayasuTsutomu Akiyama
    • G02B6/00
    • G01R31/31905
    • A test apparatus includes a test head including a plurality of test boards for applying a test pattern to a device under test, a main frame for controlling a test sequence by the test head, and a fiber optic cable unit including a plurality of flat cables for optically coupling the test head and the main frame, a plurality of fiber optic cables, a dam for coupling the fiber optic cable unit and the plurality of fiber optic cables, a circumferential difference absorption apparatus for absorbing the difference in circumferential length between the plurality of flat cables of the fiber optic cable unit, and a cable guide unit for bending and holding the fiber optic cables coupled to the test board of the main frame.
    • 测试装置包括测试头,该测试头包括用于将测试图案施加到被测设备的多个测试板,用于由测试头控制测试序列的主框架,以及包括多个扁平电缆的光缆单元, 光学耦合测试头和主框架,多根光纤电缆,用于耦合光纤电缆单元和多根光纤电缆的隔离件,用于吸收多个光纤电缆单元之间的周长差的周向差分吸收设备 光纤电缆单元的扁平电缆,以及用于弯曲和保持耦合到主框架的测试板的光纤电缆的电缆引导单元。
    • 27. 发明申请
    • Nerve regeneration promoters
    • 神经再生促进剂
    • US20070043114A1
    • 2007-02-22
    • US10574479
    • 2004-10-01
    • Narito TateishiJunki YamamotoSoichi KawaharadaTsutomu AkiyamaMasamitsu Hoshikawa
    • Narito TateishiJunki YamamotoSoichi KawaharadaTsutomu AkiyamaMasamitsu Hoshikawa
    • A61K31/557A61K31/22A61K31/20A61K31/202
    • A61K31/20A61K31/19A61K45/06
    • A nerve regeneration which comprises a compound is represented by formula (I): (wherein all symbols are shown in the description), a salt thereof or a prodrug thereof. The compound of the present invention is suppresses nerve cell death as a substance for accelerating growth and/or differentiation of stem cells (nerve stem cells, embryonic stem cells, bone marrow cells, etc.), a substance for accelerating growth and/or differentiation of nerve precursor cells, a potentiator for neurotrophic factor activity, a neurotrophic factor-like substance or a neurodegenerative suppressor, and accelerates repair and regeneration of nerve tissues by neogenesis, regeneration and/or axon evolution. In addition, the compound of the present invention is useful for preparation from brain tissues, bone marrow and/or embryonic stem cells of cells for transplant (nerve stem cells, nerve precursor cells, nerve cells, etc.) and also accelerates grafting, growth, differentiation and/or function expression of cells for transplant whereupon it is useful for prevention and/or treatment of neurodegenerative diseases.
    • 包含化合物的神经再生由式(I)表示:(其中所有符号在说明书中显示),其盐或其前药。 本发明的化合物抑制作为加速生长和/或分化的干细胞(神经干细胞,胚胎干细胞,骨髓细胞等)的生长和/或分化的物质的神经细胞死亡 的神经前体细胞,神经营养因子活性的增强剂,神经营养因子样物质或神经变性抑制剂,并通过新生,再生和/或轴突进化加速神经组织的修复和再生。 此外,本发明的化合物可用于从用于移植的细胞(神经干细胞,神经前体细胞,神经细胞等)的脑组织,骨髓和/或胚胎干细胞制备,并且还加速接枝,生长 ,用于移植的细胞的分化和/或功能表达,因此它可用于预防和/或治疗神经变性疾病。
    • 30. 发明授权
    • Self-diagnostic system for semiconductor memory
    • 半导体存储器自诊断系统
    • US5271015A
    • 1993-12-14
    • US783646
    • 1991-10-28
    • Tsutomu Akiyama
    • Tsutomu Akiyama
    • G01R31/28G11C29/00G11C29/20G11C29/46G11C29/56H01L21/66
    • G11C29/20G11C29/46
    • A self-diagnostic memory checking system includes a data generator for generating and applying data to a selected address of a memory when a CPU is in a memory write mode and generating expected data when the CPU is in a memory read mode. An address generator provides a memory address for the memory. The data is read out of the memory during the memory read mode and is compared to the expected data for detecting errors in the memory. In order to allow memory checking to proceed without constant action by software in the CPU, a range of memory addresses to be tested are loaded into a test finish detector. A separate clock generator provides enabling timing clock pulses to the address generator, data generator and memory in response to a test start signal from the CPU. A switch circuit connects data from the data generator to a first output connected to the data input of the memory when the CPU is in the memory write mode and to a second output when the CPU is the memory read mode. A comparator connected to the output of the memory for comparing the data read from the memory and to the expected data from the second output of the switch circuit gives an output representative of whether the expected data and the data read from the memory are in coincidence. A flip-flop receives the output of the comparator and indicates the result of the comparison.
    • 自诊断存储器检查系统包括数据生成器,用于当CPU处于存储器写入模式时产生和应用数据到存储器的选定地址,并且当CPU处于存储器读取模式时产生预期数据。 地址生成器为存储器提供存储器地址。 在存储器读取模式期间将数据从存储器中读出,并与用于检测存储器中的错误的期望数据进行比较。 为了允许内存检查在CPU中由软件进行不间断的动作,将要测试的一系列内存地址加载到测试完成检测器中。 单独的时钟发生器响应于来自CPU的测试开始信号,向地址发生器,数据发生器和存储器提供启用定时时钟脉冲。 当CPU处于存储器写入模式时,开关电路将来自数据发生器的数据连接到与存储器的数据输入连接的第一输出,并且当CPU是存储器读取模式时,将数据连接到第二输出。 连接到存储器的输出的比较器,用于比较从存储器读取的数据和来自开关电路的第二输出的预期数据,给出代表预期数据和从存储器读取的数据是否一致的输出。 触发器接收比较器的输出并指示比较结果。