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21. 发明专利

JPH0218771B2 失效
公开(公告)号：JPH0218771B2
公开(公告)日：1990-04-26
申请号：JP11297684
申请日：1984-06-04
申请人： HITACHI LTD
发明人： KOBORI YASUNORI , FUKUSHIMA ISAO
IPC分类号： H03K5/26

22. 发明专利

JPH0267883A VIDEO PRINTER SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH0267883A
公开(公告)日：1990-03-07
申请号：JP21969488
申请日：1988-09-02
申请人： HITACHI LTD
发明人： KIMURA HIROYUKI , HANMA KENTARO , KOBORI YASUNORI , KOMATA TAKASHI
IPC分类号： H04N5/91 , H04N1/00 , H04N1/40 , H04N1/64
摘要： PURPOSE:To reduce action speed requested of a sampling circuit by executing sampling at every other plural picture elements of a video signal. CONSTITUTION:The video signal from a display device is generated by reading picture data by a clock (n) times as much as a horizontal synchronous signal, and on the side of a printer, a phase locked loop(PLL) circuit 5 generates a picture element clock synchronously with the picture element. Here, the picture element clock is not directly used for the sampling clock input of an A/D converter 1, namely, the video signal is not sampled at every picture element unit, but at fixed interval, for example, at every N picture element. That is to say, a frequency dividing clock into which the picture element clock from the PLL circuit 5 is frequency-divided is made into a sampling clock. Thus, the high-frequency video signal can be sampled without increasing the action speed of the sampling circuit.

23. 发明专利

JPH0140550B2 失效
公开(公告)号：JPH0140550B2
公开(公告)日：1989-08-29
申请号：JP15592180
申请日：1980-11-07
申请人： HITACHI LTD
发明人： NISHIJIMA HIDEO , FUKUSHIMA ISAO , KOBORI YASUNORI
IPC分类号： H04N5/7826 , G11B15/467 , G11B27/02

24. 发明专利

JPS6490753A VIDEO PRINTER SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS6490753A
公开(公告)日：1989-04-07
申请号：JP24785187
申请日：1987-10-02
申请人： HITACHI LTD
发明人： YOSHIDA SATORU , KOBORI YASUNORI , KIMURA HIROYUKI , HANMA KENTARO
IPC分类号： B41J2/00 , B41J3/00 , H04N5/76 , H04N5/91
摘要： PURPOSE:To obtain a plurality of kinds of miniaturized image, a plurality of image of a same miniaturized image, and an enlarged image of the miniaturized image by one sheet of a print image, by providing a data miniaturization control means, a miniaturized area control means, and a frame data insertion means. CONSTITUTION:A memory means 3 is composed of a frame memory 301, a frame memory writing/reading control means 302, an address in miniaturized image area control means 303, an area address control means 304, a frame data insertion means 307, a memory and address control means 321, and an address switch 324. A first mode successively miniaturizes an image signal from a signal source 1, and keeps them in a multi state in a memory means 3. After framing process, it is confirmed with a monitor 5 and is printed by a printing means 6. A second mode selects an arbitrary one image among many image miniaturized images having been kept in the memory means 3, is enlarged respectively two times vertically horizontally to be outputted, and is processed by framing. After confirmation with the monitor 5, printing is performed.

25. 发明专利

JPS6365962B2 失效
公开(公告)号：JPS6365962B2
公开(公告)日：1988-12-19
申请号：JP8922780
申请日：1980-07-02
申请人： HITACHI LTD
发明人： KOBORI YASUNORI , NISHIJIMA HIDEO , FUKUSHIMA ISAO , GOTO KATSUHIKO
IPC分类号： G05B11/26 , G05B11/28

26. 发明专利

JPS63290754A VIDEO PRINTER 失效
公开(公告)号：JPS63290754A
公开(公告)日：1988-11-28
申请号：JP12592187
申请日：1987-05-25
申请人： HITACHI LTD
发明人： KOBORI YASUNORI , KIMURA HIROYUKI , HANMA KENTARO , GOTO TOSHIHIKO
IPC分类号： B41J2/00 , H04N1/32 , H04N1/387 , H04N5/76 , H04N5/907
摘要： PURPOSE:To enable the multi-memory and multi-print of an independent image, by a method wherein a memory control means is provided with a writing area control means controlling so that a writing is separately carried out to a memory area in the memory means by every horizontally or vertically divided halved part. CONSTITUTION:A memory means 10 is directly controlled by a W/R control means 11 and an address control means 12. A writing area of synthetic data (a memory area in the memory means 10) etc., is instructed by a memory control means 13. At this time, the position of an object in a signal source 1 is, for example, automatically and horizontally divided by a memory area control means 23. A image signal realizes various kinds of compositions due to an operation mode of the memory control means 13 and the W/R control means 11 as follows; an object is stored in a halved frame of the memory means 10, and the same frame image is printed with horizontally divided two halves; different objects are stored, and two picture planes different in field image are printed; or, vertically divided two halves enlarged crosswise can also be similarly realized by rotating a video camera as the signal source 1 by an angle of 90 deg..

27. 发明专利

JPS63266988A SIGNAL CONTROLLER FOR VIDEO PRINTER 失效
公开(公告)号：JPS63266988A
公开(公告)日：1988-11-04
申请号：JP9970587
申请日：1987-04-24
申请人： HITACHI LTD
发明人： KOBORI YASUNORI , KUDO MITSURU , KIMURA HIROYUKI , HANMA KENTARO , OKI KATSUNORI
IPC分类号： B41J2/525 , B41J2/00 , B41J3/00 , G06F3/12 , G06F3/153 , G06K15/12 , H04N9/79
摘要： PURPOSE:To share the PLL circuit of a decoding part in respective mode times by generating a memory control clock in the PLL circuit of the decoding part of the post stage of a memory at the time of the W mode and in the PLL circuit for locking a horizontal synchronization at the time of the R mode. CONSTITUTION:A composite video signal is written in a main memory 102 through an A/D converter 101. During the W period, a signal equivalent to a video signal input from an input terminal 401 is inputted to the decoding part 4 and accordingly, a signal from a PLL oscillating means 405 in the decoding part 4 is synchronized with a burst signal in the input signal in phase. This signal is supplied to the memory part 1 as a clock through a frequency multiplier 31. During the R period, a sub-carrier form a clock generating part 3 is supplied to the memory part 1 and a printer part 6 as the clock through the frequency multiplier 31.

28. 发明专利

JPS63242564A PRINTER SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS63242564A
公开(公告)日：1988-10-07
申请号：JP7402087
申请日：1987-03-30
申请人： HITACHI LTD
发明人： KIMURA HIROYUKI , KOBORI YASUNORI , HANMA KENTARO
IPC分类号： B41J2/355 , B41J2/35
摘要： PURPOSE:To enable the duplication in memory area, writing, and reading to be avoided during a high-speed printing operation, by a method wherein the writing and reading operations are changed over at fixed intervals of time even in a field unit, and a data latch circuit is provided either on the reading side or on the writing side. CONSTITUTION:An inputted original color signal or black-and-white signal is once stored in a latch circuit 2 after being subjected to A/D conversion. In reading, a read counter 7 reads a memory 3 after receiving a printing command. The data read in this manner is once latched in a latch circuit 11, thereafter being inputted to a head 13 through a halftone control circuit 12. In the head, after the data is inputted in a shift register 13a, a gate 13c is closed by the halftone control circuit 12 so that only a required line is turned ON to be heated. By carrying out this operation successively by every line, a printing image is obtained. In this manner, printing is conducted by one line by setting two frames as one cycle and changing over the areas in the memory alternately, whereby printing is enhanced in speed. In addition, at this time the slots for writing and reading are divided, whereby the duplication of timing caused by high-speed printing is avoided.

29. 发明专利

JPS63187881A VIDEO PRINTER SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS63187881A
公开(公告)日：1988-08-03
申请号：JP1833687
申请日：1987-01-30
申请人： HITACHI LTD
发明人： YOSHIDA SATORU , KIMURA HIROYUKI , KOBORI YASUNORI , HANMA KENTARO , OKI KATSUNORI
IPC分类号： B41J2/00 , B41J2/485 , B41J3/00 , H04N5/91
摘要： PURPOSE:To obtain two kinds of print pictures being the same picture as the input picture and its mirror image picture by one and the same printer by constituting either one of a write or a read address control counter by an up- down counter. CONSTITUTION:The counting method of a write pulse generating counter is switched depending on the normal print mode and the mirror image print mode to switch the phase generated for the sampling pulse. A write address control counter 9a generates an address is case of writing a print data subjected to A/D conversion by using a sampling pulse and latched in a latch circuit 5 into a line memory 8. The data read from the line memory 8 is latched once by a latch circuit 10 by using a read clock and fed to a thermosensing head 12 via a gradation control circuit 11 and printed by a density in response to each signal level. Thus, the same print picture as the monitor picture and its mirror image print picture are obtained by one and the same printer.

30. 发明专利

JPS63164697A VIDEO PRINTER SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS63164697A
公开(公告)日：1988-07-08
申请号：JP30842486
申请日：1986-12-26
申请人： HITACHI LTD
发明人： KIMURA HIROYUKI , KOBORI YASUNORI , HANMA KENTARO
IPC分类号： B41J2/525 , B41J2/00 , B41J3/00 , H04N9/79
摘要： PURPOSE:To make dot interference unnoticeable by sampling a frame in which color subscarrier wave signal starts in the positive and a frame said signal starts in the negative alternately by using a sampling frequency, or sampling only one of said two kinds of frames. CONSTITUTION:A synchronizing signal, after being separated in a synchronizing separator circuit 3, is inputted to a frame detection circuit and an oscillation circuit 4 that generates a signal whose frequency is eta times of that of a color subcarrier wave signal. In case eta=3, the frame detection circuit 7 frequency- divides a vertical synchronizing signal into four equal divisions, and transmits a signal to an AD sampling generation circuit 6 and a write address circuit 8 at the head of first frame to let them generate a sampling ck and a write address. In case of sampling at a frequency four times of that of a color subcarrier wave, a frame that starts in the positive phase is sampled twice, then a frame that starts in the negative phase is also sampled twice.

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