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21. 发明授权

US07020787B2 Microprocessor 失效
公开(公告)号：US07020787B2
公开(公告)日：2006-03-28
申请号：US10323419
申请日：2002-12-18
申请人： Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara
发明人： Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F1/32
CPC分类号： G06F9/30014 , G06F7/57
摘要： A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.

22. 发明授权

US08082429B2 Information processing apparatus and exception control circuit 有权
标题翻译：信息处理装置和异常控制电路
公开(公告)号：US08082429B2
公开(公告)日：2011-12-20
申请号：US13052281
申请日：2011-03-21
申请人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
发明人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F9/48
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3861 , G06F9/3879 , G06F9/4812 , G06F2209/481
摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.
摘要翻译：信息处理装置执行异常处理程序与正常处理之间的切换。信息处理装置包括：处理器; 数据处理单元，在从所述处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接。数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制单元判断是否使中断控制器发出中断请求以对处理器执行异常处理程序。

23. 发明申请

US20110173361A1 INFORMATION PROCESSING APPARATUS AND EXCEPTION CONTROL CIRCUIT 有权
标题翻译：信息处理设备和异常控制电路
公开(公告)号：US20110173361A1
公开(公告)日：2011-07-14
申请号：US13052281
申请日：2011-03-21
申请人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
发明人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3861 , G06F9/3879 , G06F9/4812 , G06F2209/481
摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.
摘要翻译：信息处理装置执行异常处理程序与正常处理之间的切换。信息处理装置包括：处理器; 数据处理单元，在从所述处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接。数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制单元判断是否使中断控制器发出中断请求以对处理器执行异常处理程序。

24. 发明授权

US07930520B2 Processor and program execution method capable of efficient program execution 有权
公开(公告)号：US07930520B2
公开(公告)日：2011-04-19
申请号：US12110539
申请日：2008-04-28
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30 , G06F9/44 , G06F1/32
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

25. 发明申请

US20080209192A1 PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION 有权
公开(公告)号：US20080209192A1
公开(公告)日：2008-08-28
申请号：US12110513
申请日：2008-04-28
申请人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
发明人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/22
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

26. 发明授权

US07395408B2 Parallel execution processor and instruction assigning making use of group number in processing elements 有权
标题翻译：并行执行处理器和指令分配利用处理元件中的组号
公开(公告)号：US07395408B2
公开(公告)日：2008-07-01
申请号：US10686746
申请日：2003-10-16
申请人： Takeshi Tanaka , Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara
发明人： Takeshi Tanaka , Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F15/80
CPC分类号： G06F9/3853 , G06F9/30181 , G06F9/3885 , G06F9/3887 , G06F9/3891
摘要： The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data includes two instructions, the instruction decoding unit 120 forms all the PEs into two groups, so as to assign one instruction to each group. By making it possible to execute, in parallel, not only one type of instruction but also instructions that are different from each other, it is possible to improve the utilization efficiency of the parallel execution processor 100.
摘要翻译：并行执行处理器100获取一条指令数据。当指令数据仅包含一条指令时，指令解码单元120将一条指令分配给所有PE。当指令数据包括两个指令时，指令解码单元120将所有PE形成为两组，以便为每个组分配一个指令。通过使并行执行不仅一种指令也可以彼此不同的指令成为可能，可以提高并行执行处理器100的利用效率。

27. 发明授权

US06462744B1 IMAGE DECODING APPARATUS THAT PERFORMS IMAGE DECODING SO THAT FRAME AREAS THAT OCCUPY A LARGE AREA IN A STORAGE APPARATUS CAN BE USED FOR OTHER PURPOSES, AND A RECORDING MEDIUM RECORDING AN IMAGE DECODING PROGRAM 有权
标题翻译：执行图像解码的图像解码设备，使得在存储设备中存储大面积的帧可以用于其他目的，以及记录图像解码程序的记录介质
公开(公告)号：US06462744B1
公开(公告)日：2002-10-08
申请号：US09249658
申请日：1999-02-12
申请人： Tetsuji Mochida , Tokuzo Kiyohara , Makoto Hirai , Hideshi Nishida
发明人： Tetsuji Mochida , Tokuzo Kiyohara , Makoto Hirai , Hideshi Nishida
IPC分类号： G06F1202
CPC分类号： H04N5/44508 , H04N5/4401 , H04N5/44504 , H04N19/423 , H04N19/61 , H04N21/4435
摘要： When an OSD data storage area for storing OSD data needs to be reserved, an area of a frame storage apparatus that should store macroblocks corresponding to an invisible area on a screen is allocated as the OSD data storage area. There is no degradation in picture quality. When doing so, the data reduction control unit 64 receives an instruction to reserve the OSD data storage area and discards the corresponding macroblocks. The OSD data access unit 63 writes the OSD data into an area of the frame storage apparatus that was assigned to store the discarded macroblocks.
摘要翻译：当需要保留用于存储OSD数据的OSD数据存储区域时，将存储与屏幕上不可见区域相对应的宏块的帧存储装置的区域分配为OSD数据存储区域。图像质量没有降低。当这样做时，数据缩减控制单元64接收保留OSD数据存储区域的指令并丢弃对应的宏块。 OSD数据存取单元63将OSD数据写入分配给存储被丢弃的宏块的帧存储装置的区域。

28. 发明授权

US07594099B2 Processor executing SIMD instructions 有权
标题翻译：处理器执行SIMD指令
公开(公告)号：US07594099B2
公开(公告)日：2009-09-22
申请号：US11896368
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/305
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC0〜VC3（110）全部为零，并且（i）设置条件标志C4 当所有向量条件标志VC0〜VC3都为零时，分别将条件标志寄存器（CFR）32至1和0分别设置为条件标志寄存器（CFR）32和C5，以及（ii）分别将条件标志C4和C5设置为0和1，并非所有向量条件标志都为零。然后，矢量条件标志VC0〜VC3被存储在条件标志C0〜C3中。

29. 发明申请

US20080046704A1 Processor executing SIMD instructions 审中-公开
标题翻译：处理器执行SIMD指令
公开(公告)号：US20080046704A1
公开(公告)日：2008-02-21
申请号：US11896371
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki OKabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki OKabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/38
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

30. 发明授权

US10230991B2 Signal-processing apparatus including a second processor that, after receiving an instruction from a first processor, independantly controls a second data processing unit without further instrcuction from the first processor 有权
公开(公告)号：US10230991B2
公开(公告)日：2019-03-12
申请号：US12179873
申请日：2008-07-25
申请人： Tomonori Kataoka , Hideshi Nishida , Kouzou Kimura , Nobuo Higaki , Tokuzo Kiyohara
发明人： Tomonori Kataoka , Hideshi Nishida , Kouzou Kimura , Nobuo Higaki , Tokuzo Kiyohara
IPC分类号： G06F9/38 , H04N19/86 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/436 , H04N19/523
摘要： A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

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