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21. 发明申请

US20070237015A1 Semiconductor memory device and dynamic latch refresh method thereof 有权
标题翻译：半导体存储器件及其动态锁存刷新方法
公开(公告)号：US20070237015A1
公开(公告)日：2007-10-11
申请号：US11510733
申请日：2006-08-28
申请人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
发明人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G11C16/0483 , G11C29/70 , G11C29/832 , G11C2211/565 , H01L27/105 , H01L27/115
摘要： A semiconductor integrated circuit device includes dynamic latches, switch circuit, capacitor, first static latch, and first transfer gate. In refreshing data of the dynamic latches, data stored in the first static latch is moved to the second node through the first transfer gate and saved. The data of the dynamic latch is bootstrapped. The bootstrapped data is transferred to the first node to distribute charges, thereby setting the potential of the first node. The set potential is written back to the dynamic latch to refresh it. The saved data of the second node is moved to the first node through the first transfer gate and written back to the first static latch.
摘要翻译：半导体集成电路器件包括动态锁存器，开关电路，电容器，第一静态锁存器和第一传输门。在动态锁存器的刷新数据中，存储在第一静态锁存器中的数据通过第一传送门移动到第二节点并被保存。动态锁存器的数据被自举。自举数据被传送到第一节点以分配费用，从而设置第一节点的电位。设置电位被写回到动态锁存器来刷新它。第二节点的保存数据通过第一传输门移动到第一节点并写回到第一静态锁存器。

22. 发明申请

US20110149653A1 NAND FLASH MEMORY 有权
标题翻译： NAND闪存
公开(公告)号：US20110149653A1
公开(公告)日：2011-06-23
申请号：US13037965
申请日：2011-03-01
申请人： Hiroshi MAEJIMA , Katsuaki Isobe
发明人： Hiroshi MAEJIMA , Katsuaki Isobe
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
摘要翻译：读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中高于所述接地电位，并且等于或低于所述第二电压。

23. 发明申请

US20080094903A1 NAND FLASH MEMORY 有权
标题翻译： NAND闪存
公开(公告)号：US20080094903A1
公开(公告)日：2008-04-24
申请号：US11873859
申请日：2007-10-17
申请人： Hiroshi Maejima , Katsuaki Isobe
发明人： Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
摘要翻译：读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中高于所述接地电位，并且等于或低于所述第二电压。

24. 发明授权

US08630116B2 NAND flash memory 有权
标题翻译： NAND闪存
公开(公告)号：US08630116B2
公开(公告)日：2014-01-14
申请号：US13633553
申请日：2012-10-02
申请人： Hiroshi Maejima , Katsuaki Isobe
发明人： Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
摘要翻译：读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中高于所述接地电位，并且等于或低于所述第二电压。

25. 发明授权

US07518922B2 NAND type flash memory 有权
标题翻译： NAND型闪存
公开(公告)号：US07518922B2
公开(公告)日：2009-04-14
申请号：US11749214
申请日：2007-05-16
申请人： Hiroshi Maejima , Katsuaki Isobe , Takumi Abe , Ken Takeuchi
发明人： Hiroshi Maejima , Katsuaki Isobe , Takumi Abe , Ken Takeuchi
IPC分类号： G11C16/04
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/12 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C2211/5646 , G11C2211/5647
摘要： A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on the number of the “1” data and the “0” data of the data when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.
摘要翻译： NAND型闪速存储器，包括由以矩阵形状排列的多个电子可重写存储单元组成的存储单元阵列;以及数据反转控制单元，判定“1”数据或“0”数据的极性是否为当数据被发送到同时写入数据单元内的多个存储单元时，基于“1”数据和“0”数据的数字被反转，并且反转数据，并且在发送的情况下到存储单元阵列向显示极性反转的数据添加反转标志位。

26. 发明授权

US08300466B2 NAND flash memory 有权
标题翻译： NAND闪存
公开(公告)号：US08300466B2
公开(公告)日：2012-10-30
申请号：US13037965
申请日：2011-03-01
申请人： Hiroshi Maejima , Katsuaki Isobe
发明人： Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
摘要翻译：读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中高于所述接地电位，并且等于或低于所述第二电压。

27. 发明申请

US20100097860A1 NAND FLASH MEMORY 有权
标题翻译： NAND闪存
公开(公告)号：US20100097860A1
公开(公告)日：2010-04-22
申请号：US12642503
申请日：2009-12-18
申请人： Hiroshi MAEJIMA , Katsuaki Isobe
发明人： Hiroshi MAEJIMA , Katsuaki Isobe
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.
摘要翻译：读取操作中的NAND闪速存储器设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电位于接地电位和第一电压之间的第二电压，并且在未被所述行解码器选择的块中，所述漏极侧选择栅极线和所述源极侧选择栅极线被充电到第三电压，其中高于所述接地电位，并且等于或低于所述第二电压。

28. 发明授权

US07660157B2 NAND flash memory 有权
标题翻译： NAND闪存
公开(公告)号：US07660157B2
公开(公告)日：2010-02-09
申请号：US11873859
申请日：2007-10-17
申请人： Hiroshi Maejima , Katsuaki Isobe
发明人： Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/0483
摘要： A NAND flash memory, including a memory cell array, a row decoder, and a sense amplifier. In a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by the row decoder, a drain-side select gate line and the source-side select gate line are charged to a third voltage, which is higher than the ground potential and is equal to or lower than the second voltage.
摘要翻译：一种NAND闪存，包括存储单元阵列，行解码器和读出放大器。在读取操作中，将p型半导体衬底设置为接地电位，将位线充电至第一电压，将源极线，n型阱和p型阱充电至第二电压，位于接地电位和第一电压之间，并且在未被行解码器选择的块中，漏极侧选择栅极线和源极侧选择栅极线被充电到高于地的第三电压并且等于或低于第二电压。

29. 发明授权

US07388790B2 Semiconductor memory device and dynamic latch refresh method thereof 有权
标题翻译：半导体存储器件及其动态锁存刷新方法
公开(公告)号：US07388790B2
公开(公告)日：2008-06-17
申请号：US11510733
申请日：2006-08-28
申请人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
发明人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/0483 , G11C29/70 , G11C29/832 , G11C2211/565 , H01L27/105 , H01L27/115
摘要： A semiconductor integrated circuit device includes dynamic latches, switch circuit, capacitor, first static latch, and first transfer gate. In refreshing data of the dynamic latches, data stored in the first static latch is moved to the second node through the first transfer gate and saved. The data of the dynamic latch is bootstrapped. The bootstrapped data is transferred to the first node to distribute charges, thereby setting the potential of the first node. The set potential is written back to the dynamic latch to refresh it. The saved data of the second node is moved to the first node through the first transfer gate and written back to the first static latch.
摘要翻译：半导体集成电路器件包括动态锁存器，开关电路，电容器，第一静态锁存器和第一传输门。在动态锁存器的刷新数据中，存储在第一静态锁存器中的数据通过第一传送门移动到第二节点并被保存。动态锁存器的数据被自举。自举数据被传送到第一节点以分配费用，从而设置第一节点的电位。设置电位被写回到动态锁存器来刷新它。第二节点的保存数据通过第一传输门移动到第一节点并写回到第一静态锁存器。

30. 发明申请

US20110235417A1 NAND FLASH MEMORY 审中-公开
标题翻译： NAND闪存
公开(公告)号：US20110235417A1
公开(公告)日：2011-09-29
申请号：US13154522
申请日：2011-06-07
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C16/02
CPC分类号： G11C8/08 , G11C8/10 , G11C16/0483
摘要： A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state.
摘要翻译：在选择的位线和非选择的位线彼此相邻时读取的NAND快闪存储器具有存储单元阵列，其具有多个块，每个块由多个存储单元单元组成，每个块由多个存储单元单元组成所述存储单元具有多个电可重写存储单元，它们彼此连接并且由形成在p型半导体衬底中的n型阱围绕的p型阱组成，每个漏极侧选择栅晶体管其将存储单元单元连接到位线并连接到其栅极处的漏极侧选择栅极线，以及源极选择栅极晶体管，每个源极选择栅极晶体管将存储单元单元连接到源极线并连接到源极选择栅极线; 连接到所述存储单元阵列的字线，漏极侧选择栅极线和源极侧栅极线的行解码器，并将信号电压施加到字线，漏极侧选择栅极线和源极侧选择栅极线，所述存储单元阵列的侧栅极线用于选择块; 以及由列解码器控制并从所述存储单元阵列的所述位线进行选择的读出放大器，其中，在未被所述行解码器选择的块中，由所述读出放大器选择的所述位线被充电漏极侧选择栅极线，源极侧选择栅极线和p型半导体衬底设置为接地电位的状态，源极线，n型阱，p型阱和a 未被所述读出放大器选择的位线处于浮置状态。

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