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21. 发明授权

US5870129A Image forming method and apparatus transferring an ink image 失效
标题翻译：图像形成方法和设备转印墨像
公开(公告)号：US5870129A
公开(公告)日：1999-02-09
申请号：US713503
申请日：1996-09-13
申请人： Akihito Ikegawa , Hiroyuki Yamasaki
发明人： Akihito Ikegawa , Hiroyuki Yamasaki
IPC分类号： G03G9/18 , G03G13/10 , G03G15/16 , G03G15/22 , B41J2/385 , G03G9/08 , G03G15/00
CPC分类号： G03G9/18 , G03G13/10 , G03G15/169 , G03G15/228
摘要： An image forming method according to the present invention comprises the steps of forming an electrostatic latent image on an image carrying member by a latent image forming device, applying a release agent to the surface of the image carrying member by an application device, and bringing an ink carried on an ink carrying member into contact with the surface of the image carrying member coated with the release agent to form an ink image corresponding to the electrostatic latent image on the surface of the image carrying member.
摘要翻译：根据本发明的图像形成方法包括以下步骤：通过潜像形成装置在图像承载构件上形成静电潜像，通过施加装置将防粘剂施加到图像承载构件的表面，并使携带在墨承载构件上的油墨与涂覆有脱模剂的图像承载构件的表面接触以形成对应于图像承载构件表面上的静电潜像的油墨图像。

22. 发明授权

US5568244A Image forming apparatus including an endless transfer member 失效
标题翻译：图像形成装置，包括环形传送构件
公开(公告)号：US5568244A
公开(公告)日：1996-10-22
申请号：US355289
申请日：1994-12-12
申请人： Atsuto Hirai , Masahide Ueda , Yoshihisa Terasaka , Eiichi Sano , Masahiko Matsuura , Hiroyuki Yamasaki , Masami Yamada , Tomoo Izumi
发明人： Atsuto Hirai , Masahide Ueda , Yoshihisa Terasaka , Eiichi Sano , Masahiko Matsuura , Hiroyuki Yamasaki , Masami Yamada , Tomoo Izumi
IPC分类号： G03G15/01 , G03G15/16 , G03G21/00
CPC分类号： B82Y15/00 , G03G15/0131 , G03G15/167 , G03G2215/0174
摘要： An image forming apparatus for forming an image onto a sheet includes a sheet supporting member; a charger which is positioned in a vicinity of the sheet supporting member; and a device for controlling the charger so that the charger charges a specific portion of the sheet supporting member corresponding to a leading edge portion of the sheet to an electrostatic potential higher than that of a remaining portion of the sheet supporting member. A method of adhering a sheet to a sheet supporting member during an image forming process includes charging a specific portion of the sheet supporting member corresponding to a leading edge portion of the sheet to a first electrostatic potential; charging a remaining portion of the sheet supporting member to a second electrostatic potential that is lower than the first electrostatic potential; and delivering the sheet to the sheet supporting member so that a leading edge portion of the sheet is aligned with the specific portion of the sheet supporting member.
摘要翻译：用于在片材上形成图像的图像形成装置包括片材支撑构件; 位于所述片材支撑构件附近的充电器; 以及用于控制充电器的装置，使得充电器将对应于片材的前缘部分的片材支撑构件的特定部分充电到高于片材支撑构件的剩余部分的静电势。在图像形成处理中将片材粘贴到片材支撑构件的方法包括将对应于片材的前缘部分的片材支撑构件的特定部分充电到第一静电电位; 将片材支撑构件的剩余部分充电至低于第一静电电位的第二静电电位; 并将片材输送到片材支撑构件，使得片材的前缘部分与片材支撑构件的特定部分对准。

23. 发明授权

US4843596A Semiconductor memory device with address transition detection and timing control 失效
标题翻译：具有地址转换检测和定时控制的半导体存储器件
公开(公告)号：US4843596A
公开(公告)日：1989-06-27
申请号：US124554
申请日：1987-11-24
申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
发明人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
IPC分类号： G11C11/401 , G11C7/22 , G11C8/18
CPC分类号： G11C8/18 , G11C7/22
摘要： A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.
摘要翻译：一种新颖的半导体存储器件包括响应于地址变化的检测而产生短宽度脉冲的地址检测电路。列解码器激活信号发生器检测短宽度脉冲的开始，并且响应于产生列解码器激活信号。第二检测电路检测短宽度脉冲的结论，并产生触发前置放大器激活信号的第二脉冲，其激活前置放大器并锁存输入/输出线上存在的数据。复位信号发生器产生复位信号以停用列解码器激活信号并延迟前置放大器激活信号。当输出第一个脉冲时，前置放大器激活信号发生器和复位信号发生器被复位。

24. 发明授权

US4823322A Dynamic random access memory device having an improved timing arrangement 失效
标题翻译：具有改进的定时布置的动态随机存取存储器件
公开(公告)号：US4823322A
公开(公告)日：1989-04-18
申请号：US102683
申请日：1987-09-30
申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
发明人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Yasuhiro Konishi , Katsumi Dosaka , Hiroyuki Yamasaki , Masaki Shimoda , Yuto Ikeda , Kazuhiro Tsukamoto
IPC分类号： G11C11/407 , G11C11/401 , G11C11/4076 , G11C11/409 , G11C11/413 , G11C7/00
CPC分类号： G11C11/4076
摘要： A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.
摘要翻译：具有连接在一对输入/输出线之间的输入/输出负载和用于产生内部/ RAS信号的动态随机存取存储器件，该内部/ RAS信号具有相对于外部/ RAS信号的相同转变延迟的复位转变。内部/ RAS信号至少控制施加到所选择的存储单元的晶体管的字信号和施加到使能晶体管的使能信号，从而使存储器单元和使能晶体管变为不导通的时间被延迟相对于连接在每对位线和输入/输出线之间的传输晶体管的时间变得不导通。

25. 发明申请

US20130270614A1 FORMATION OF A TRENCH SILICIDE 审中-公开
标题翻译：形成硅胶
公开(公告)号：US20130270614A1
公开(公告)日：2013-10-17
申请号：US13448513
申请日：2012-04-17
申请人： Hiroyuki Yamasaki
发明人： Hiroyuki Yamasaki
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/28518 , H01L21/76814 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L29/665 , H01L29/78
摘要： Systems and methods are presented for controlling formation of a silicide region. A selective etch layer is utilized to control formation of a trench opening, and further can be utilized to open up a trench to facilitate correct exposure of an active Si region to subsequently form a silicide. Issues regarding over-dimension, under-dimension, and misalignment of a trench are addressed. The selective etch material is chosen to facilitate control of the trench formation and also to enable removal of the selective etch layer without affecting any adjacent structures/material. The selective etch layer can be an oxide, for example aluminum oxide, Al2O3. The selective etch layer can be utilized to prevent formation of silicide in a channel beneath a raised source/drain.
摘要翻译：呈现用于控制硅化物区域的形成的系统和方法。使用选择性蚀刻层来控制沟槽开口的形成，并且还可以用于打开沟槽以促进有源Si区域的正确曝光以随后形成硅化物。关于沟槽尺寸过大，尺寸不合格和未对准的问题得到了解决。选择性蚀刻材料被选择以便于控制沟槽形成，并且还能够去除选择性蚀刻层而不影响任何相邻的结构/材料。选择性蚀刻层可以是氧化物，例如氧化铝，Al 2 O 3。选择性蚀刻层可用于防止在升高的源极/漏极下方的沟道中形成硅化物。

26. 发明申请

US20120241866A1 TRANSISTOR STRUCTURE AND MANUFACTURING METHOD WHICH HAS CHANNEL EPITAXIAL EQUIPPED WITH LATERAL EPITAXIAL STRUCTURE 审中-公开
标题翻译：具有侧向外延结构的通道外形的晶体管结构和制造方法
公开(公告)号：US20120241866A1
公开(公告)日：2012-09-27
申请号：US13070561
申请日：2011-03-24
申请人： Hiroyuki Yamasaki
发明人： Hiroyuki Yamasaki
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L27/1104 , H01L21/28123 , H01L21/76232 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/66651 , H01L29/78
摘要： A semiconductor device and methods of fabricating semiconductor devices are provided. Provided is an epitaxial layer equipped with a lateral epitaxial layer that can block a Shallow Trench Isolation (STI) edge from a downstream etching process step, which can result in a reduced STI divot. A method involves forming a semiconductor substrate on a source region and a drain region and forming a semiconductor region on the semiconductor substrate. The method also comprises creating at least a first isolation feature adjacent to the semiconductor region and depositing an epitaxial layer on the semiconductor region and laterally between the semiconductor region and the at least the first isolation feature.
摘要翻译：提供半导体器件和制造半导体器件的方法。提供了一种外延层，其具有可以从下游蚀刻工艺步骤阻挡浅沟槽隔离（STI）边缘的横向外延层，这可能导致STI纹路减小。一种方法包括在源区和漏区上形成半导体衬底，并在半导体衬底上形成半导体区。该方法还包括至少创建与半导体区域相邻的第一隔离特征，并在半导体区域上以及在半导体区域与至少第一隔离特征之间横向地沉积外延层。

27. 发明授权

US07489617B2 Optical head and optical head device 失效
标题翻译：光头和光头设备
公开(公告)号：US07489617B2
公开(公告)日：2009-02-10
申请号：US11489484
申请日：2006-07-20
申请人： Hiroyuki Yamasaki , Yasushi Kobayashi , Manami Kuiseko
发明人： Hiroyuki Yamasaki , Yasushi Kobayashi , Manami Kuiseko
IPC分类号： G11B7/00
CPC分类号： G11B7/1387 , G11B7/1359 , G11B7/1362 , G11B7/1384
摘要： An optical head which has a prism with an incident section, an internal reflective surface and an emergent surface, and an optical head device which employs the optical head. Light emitted from a light source is incident to the prism through the incident section, reflects at least once on the internal reflective surface and is converged in the vicinity of the emergent surface. Then, the light effuses through the emergent surface as near field light.
摘要翻译：具有入射部分的棱镜，内部反射表面和出射表面的光学头，以及使用该光学头的光学头装置。从光源发射的光通过入射部入射到棱镜，至少在内反射面上反射一次并会聚到出射面附近。然后，光通过出射表面流过近场光。

28. 发明授权

US07394120B2 Semiconductor device having a shaped gate electrode and method of manufacturing the same 失效
标题翻译：具有成形栅电极的半导体器件及其制造方法
公开(公告)号：US07394120B2
公开(公告)日：2008-07-01
申请号：US11146029
申请日：2005-06-07
申请人： Hiroyuki Yamasaki , Hitoshi Ito
发明人： Hiroyuki Yamasaki , Hitoshi Ito
IPC分类号： H01L29/78
CPC分类号： H01L29/4238 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： An MIS transistor includes a gate electrode located to intersect a device region of a semiconductor substrate isolated by a device isolation region, and source and drain regions formed in the semiconductor substrate at both sides of the gate electrode region and elevated source and drain located above the source and drain regions. A gate length of the gate electrode at a boundary between the device isolation region and the device region is longer than the gate length at a central portion of the device region.
摘要翻译： MIS晶体管包括位于与器件隔离区隔离的半导体衬底的器件区域相交的栅电极，以及形成在栅电极区两侧的半导体衬底中的源区和漏区以及位于源极和漏极区域。在器件隔离区域和器件区域之间的边界处的栅电极的栅极长度大于器件区域的中心部分处的栅极长度。

29. 发明申请

US20060256697A1 Optical head and optical head device 失效
公开(公告)号：US20060256697A1
公开(公告)日：2006-11-16
申请号：US11489484
申请日：2006-07-20
申请人： Hiroyuki Yamasaki , Yasushi Kobayashi , Manami Kuiseko
发明人： Hiroyuki Yamasaki , Yasushi Kobayashi , Manami Kuiseko
IPC分类号： G11B7/00
CPC分类号： G11B7/1387 , G11B7/1359 , G11B7/1362 , G11B7/1384
摘要： An optical head which has a prism with an incident section, an internal reflective surface and an emergent surface, and an optical head device which employs the optical head. Light emitted from a light source is incident to the prism through the incident section, reflects at least once on the internal reflective surface and is converged in the vicinity of the emergent surface. Then, the light effuses through the emergent surface as near field light.

30. 发明申请

US20060071260A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060071260A1
公开(公告)日：2006-04-06
申请号：US11235063
申请日：2005-09-27
申请人： Hiroyuki Yamasaki
发明人： Hiroyuki Yamasaki
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L29/945 , H01L27/10867
摘要： A semiconductor device includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, the insulating film including an opening portion, a surface strap embedded in the opening portion, the surface strap comprising a semiconductor layer, a reaction preventing film provided on the surface strap, the reaction preventing film comprising a material different from that of the insulating film, a storage electrode of a trench capacitor provided in the semiconductor substrate, the storage electrode connecting electrically with the surface strap, and a source/drain region provided on a surface of the semiconductor substrate, the source/drain region connecting electrically with the storage electrode via the surface strap.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底上的绝缘膜，绝缘膜包括开口部分，嵌入在开口部分中的表面带，表面带包括半导体层，反应防止膜设置在表面上带，反应防止膜包括与绝缘膜不同的材料，设置在半导体衬底中的沟槽电容器的存储电极，与表面带电连接的存储电极和设置在表面上的源极/漏极区域所述源极/漏极区域经由所述表面带与所述存储电极电连接。

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