专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20090017640A1 BORON DERIVED MATERIALS DEPOSITION METHOD 有权
标题翻译： BORON衍生材料沉积方法
公开(公告)号：US20090017640A1
公开(公告)日：2009-01-15
申请号：US12171783
申请日：2008-07-11
申请人： Jeong-Uk Huh , Mihaela Balseanu , Li-Qun Xia , Derek R. Witty , Hichem M'Saad
发明人： Jeong-Uk Huh , Mihaela Balseanu , Li-Qun Xia , Derek R. Witty , Hichem M'Saad
IPC分类号： H01L21/469 , B05D3/02 , H05H1/00 , C08F2/46
CPC分类号： C23C16/28 , C23C16/56 , H01L21/314 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： Methods of forming boron-containing films are provided. The methods include introducing a boron-containing precursor into a chamber and depositing a network comprising boron-boron bonds on a substrate by thermal decomposition or a plasma process. The network may be post-treated to remove hydrogen from the network and increase the stress of the resulting boron-containing film. The boron-containing films have a stress between about −10 GPa and 10 GPa and may be used as boron source layers or as strain-inducing layers.
摘要翻译：提供形成含硼膜的方法。所述方法包括将含硼前体引入室中，并通过热分解或等离子体处理将包含硼 - 硼键的网络沉积在衬底上。可以对网络进行后处理以从网络中除去氢，并增加所得含硼膜的应力。含硼膜的应力在约-10GPa和10GPa之间，可用作硼源层或应变诱导层。

22. 发明授权

US07425716B2 Method and apparatus for reducing charge density on a dielectric coated substrate after exposure to a large area electron beam 失效
标题翻译：用于在暴露于大面积电子束之后降低电介质涂覆的基底上的电荷密度的方法和装置
公开(公告)号：US07425716B2
公开(公告)日：2008-09-16
申请号：US11414649
申请日：2006-04-27
申请人： Alexandros T. Demos , Khaled A. Elsheref , Yuri Trachuk , Tom K. Cho , Girish A. Dixit , Hichem M'Saad , Derek Witty
发明人： Alexandros T. Demos , Khaled A. Elsheref , Yuri Trachuk , Tom K. Cho , Girish A. Dixit , Hichem M'Saad , Derek Witty
IPC分类号： H02H23/00
CPC分类号： H01J37/317 , H01J2237/0041
摘要： Embodiments in accordance with the present invention relate to a number of techniques, which may be applied alone or in combination, to reduce charge damage of substrates exposed to electron beam radiation. In one embodiment, charge damage is reduced by establishing a robust electrical connection between the exposed substrate and ground. In another embodiment, charge damage is reduced by modifying the sequence of steps for activating and deactivating the electron beam source to reduce the accumulation of charge on the substrate. In still another embodiment, a plasma is struck in the chamber containing the e-beam treated substrate, thereby removing accumulated charge from the substrate. In a further embodiment of the present invention, the voltage of the anode of the e-beam source is reduced in magnitude to account for differences in electron conversion efficiency exhibited by different cathode materials.
摘要翻译：根据本发明的实施例涉及可以单独或组合应用的多种技术，以减少暴露于电子束辐射的衬底的电荷损伤。在一个实施例中，通过在暴露的基板和地之间建立牢固的电连接来减小电荷损伤。在另一个实施例中，通过修改用于激活和去激活电子束源的步骤顺序来减少电荷损伤，以减少电荷在衬底上的累积。在另一个实施例中，在包含电子束处理的衬底的室中撞击等离子体，从而从衬底去除积聚的电荷。在本发明的另一个实施例中，电子束源的阳极的电压的大小被减小以考虑到由不同的阴极材料表现的电子转换效率的差异。

23. 发明申请

US20080107573A1 METHOD FOR FORMING AN ULTRA LOW DIELECTRIC FILM BY FORMING AN ORGANOSILICON MATRIX AND LARGE POROGENS AS A TEMPLATE FOR INCREASED POROSITY 审中-公开
公开(公告)号：US20080107573A1
公开(公告)日：2008-05-08
申请号：US11877390
申请日：2007-10-23
申请人： Francimar Schmitt , Hichem M'Saad
发明人： Francimar Schmitt , Hichem M'Saad
IPC分类号： B01J19/00
CPC分类号： H01L21/76825 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02351 , H01L21/02362 , H01L21/3122 , H01L21/31695 , H01L21/76811 , H01L21/76813 , H01L21/7682 , H01L2221/1047
摘要： Ultra low K nanoporous dielectric films may be formed by chemical vapor deposition of silicon-containing components and large non-silicon containing porogens having labile groups. In accordance with one embodiment of the present invention, a low K nanoporous film may be formed by the oxidative reaction between trimethylsilane (the silicon-containing component) and alpha-terpinene (the non-silicon containing component). In accordance with certain embodiments of the present invention, the oxidant can comprise other than molecular oxygen, for example water vapor introduced in-situ or remotely, and then exposed to RF energy to generate reactive ionic species.

24. 发明申请

US20080014761A1 Decreasing the etch rate of silicon nitride by carbon addition 有权
标题翻译：通过碳添加降低氮化硅的蚀刻速率
公开(公告)号：US20080014761A1
公开(公告)日：2008-01-17
申请号：US11478273
申请日：2006-06-29
申请人： Ritwik Bhatia , Li-Qun Xia , Chad Peterson , Hichem M'Saad
发明人： Ritwik Bhatia , Li-Qun Xia , Chad Peterson , Hichem M'Saad
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/0332 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/3185 , H01L21/76825 , H01L21/76829
摘要： Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.
摘要翻译：提供了形成氮化硅硬掩模的方法。氮化硅硬掩模包括碳掺杂的氮化硅层和未掺杂的氮化硅层。提供了在RF功率存在下从包含碳源化合物，硅源化合物和氮源的混合物沉积的碳掺杂氮化硅层。还提供了UV后处理氮化硅层以提供氮化硅硬掩模的方法。碳掺杂的氮化硅层和UV后处理的氮化硅层对于硬掩模层具有期望的湿蚀刻速率和干蚀刻速率。

25. 发明申请

US20070232082A1 METHOD TO IMPROVE THE STEP COVERAGE AND PATTERN LOADING FOR DIELECTRIC FILMS 有权
标题翻译：用于改进电介质膜的步骤覆盖和图案加载的方法
公开(公告)号：US20070232082A1
公开(公告)日：2007-10-04
申请号：US11668911
申请日：2007-01-30
申请人： Mihaela Balseanu , Meiyee Shek , Li-Qun Xia , Hichem M'Saad
发明人： Mihaela Balseanu , Meiyee Shek , Li-Qun Xia , Hichem M'Saad
IPC分类号： H01L21/469
CPC分类号： H01L21/76834 , H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/0228 , H01L21/31612 , H01L21/31633 , H01L21/76829 , H01L21/76831
摘要： A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.
摘要翻译：提供了一种在室中的衬底上形成层的方法，其中衬底在其表面上具有至少一个形成的特征。该方法包括在存在等离子体的情况下将衬底暴露于含硅前体以沉积一层，用等离子体处理沉积层，并重复曝光和处理，直到获得所需层厚。等离子体可以由含氧气体产生。

26. 发明申请

US20070202640A1 Low-k spacer integration into CMOS transistors 审中-公开
标题翻译：低k隔离器集成到CMOS晶体管中
公开(公告)号：US20070202640A1
公开(公告)日：2007-08-30
申请号：US11365740
申请日：2006-02-28
申请人： Amir Al-Bayati , Reza Arghavani , Mei-Yee Shek , Li-Qun Xia , Mihaela Balseanu , Bok Kim , Michael Cox , Chad Peterson , Hichem M'Saad
发明人： Amir Al-Bayati , Reza Arghavani , Mei-Yee Shek , Li-Qun Xia , Mihaela Balseanu , Bok Kim , Michael Cox , Chad Peterson , Hichem M'Saad
IPC分类号： H01L21/338
CPC分类号： H01L29/4983 , H01L21/02115 , H01L21/02126 , H01L21/0217 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02362 , H01L21/26586 , H01L21/3146 , H01L21/31633 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： A method of forming source and drain regions in a semiconductor transistor. The method includes the steps of forming a first sidewall spacer on sidewall surfaces of a gate electrode that is formed on an underlying substrate, where the first sidewall spacer includes amorphous carbon. The method may also include implanting the source and drain regions in the semiconductor substrate, and removing the first sidewall spacer before annealing the source and drain regions. The method may still further include forming a second sidewall spacer on the sidewall surfaces of the gate electrode, where the second sidewall spacer has a k-value less than 4. Also, a method to enhance conformality of a sidewall spacer layer. The method may include the steps of pulsing a radio-frequency power source to generate periodically a plasma, and depositing the plasma on sidewall surfaces of a gate electrode to form the sidewall spacer layer.
摘要翻译：一种在半导体晶体管中形成源区和漏区的方法。该方法包括以下步骤：在形成在下面的基底上的栅电极的侧壁表面上形成第一侧壁间隔物，其中第一侧壁间隔物包括无定形碳。该方法还可以包括将源极和漏极区域注入到半导体衬底中，以及在退火源极和漏极区域之前去除第一侧壁间隔物。该方法还可以包括在栅电极的侧壁表面上形成第二侧壁间隔物，其中第二侧壁间隔物的k值小于4.另外，增强侧壁间隔层的一致性的方法。该方法可以包括以下步骤：脉冲射频电源周期性地产生等离子体，以及将等离子体沉积在栅电极的侧壁表面上以形成侧壁间隔层。

27. 发明申请

US20070132054A1 MEMORY CELL HAVING STRESSED LAYERS 失效
标题翻译：具有压力层的记忆体
公开(公告)号：US20070132054A1
公开(公告)日：2007-06-14
申请号：US11609851
申请日：2006-12-12
申请人： Reza Arghavani , Ellie Yieh , Hichem M'Saad
发明人： Reza Arghavani , Ellie Yieh , Hichem M'Saad
IPC分类号： H01L29/00
CPC分类号： H01L29/7846 , H01L27/105 , H01L27/1052 , H01L29/66825 , H01L29/7883
摘要： A memory cell comprises a p-doped substrate with a pair of spaced apart n-doped regions on the substrate that form a source and drain about the channel. A stack of layers on the channel comprises, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate. A polysilicon layer is on the source and drain. A cover layer covering the stack of layers comprises a spacer layer and a pre-metal-deposition layer. Optionally, contacts are used to contact each of the source, drain, and silicide layers, and each have exposed portions. A shallow isolation trench is provided about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa. The stressed layer reduces leakage of charge held in the floating gate during operation of the memory cell.
摘要翻译：存储单元包括在基板上具有一对间隔开的n掺杂区域的p掺杂衬底，其在沟道周围形成源极和漏极。通道上的层叠层包括（i）隧道氧化物层，（ii）浮动栅极，（iii）栅极间电介质和（iv）控制栅极。源极和漏极上的多晶硅层。覆盖层叠层的覆盖层包括间隔层和预金属沉积层。可选地，使用触点来接触源极，漏极和硅化物层中的每一个，并且每个都具有暴露部分。围绕n掺杂区域提供浅的隔离沟槽，沟槽包括具有至少约200MPa的拉伸应力的应力氧化硅层。应力层在存储器单元的操作期间减少了保持在浮动栅极中的电荷的泄漏。

28. 发明申请

US20070079753A1 Method To Deposit Functionally Graded Dielectric Films Via Chemical Vapor Deposition Using Viscous Precursors 有权
标题翻译：通过使用粘性前体的化学气相沉积来沉积功能性梯度介电膜的方法
公开(公告)号：US20070079753A1
公开(公告)日：2007-04-12
申请号：US11608333
申请日：2006-12-08
申请人： Deenesh Padhi , Sohyun Park , Ganesh Balasubramanian , Juan Rocha-Alvarez , Li-Qun Xia , Derek Witty , Hichem M'Saad
发明人： Deenesh Padhi , Sohyun Park , Ganesh Balasubramanian , Juan Rocha-Alvarez , Li-Qun Xia , Derek Witty , Hichem M'Saad
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： H01L21/31633 , C23C16/029 , C23C16/401 , C23C16/45523 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/76841
摘要： A method of forming a graded dielectric layer on an underlying layer including flowing a mixture of a silicon-carbon containing gas, an oxygen containing gas and a carrier gas through a showerhead comprising a blocking plate and a faceplate to form an oxide rich portion of the graded dielectric layer, where the silicon-carbon containing gas has an initial flow rate, flowing the silicon-carbon containing gas at a first intermediate flow rate for about 0.5 seconds or longer, where the first intermediate flow rate is higher than the initial flow rate, and flowing the silicon-carbon containing gas at a fastest flow rate higher than the first intermediate flow rate to form a carbon rich portion of the graded dielectric layer.
摘要翻译：一种在下层上形成渐变电介质层的方法，包括使含硅碳的气体，含氧气体和载体气体的混合物流过包括阻挡板和面板的喷头，以形成氧化物富集部分其中含硅碳的气体具有初始流速，使含硅碳的气体以第一中间流速流动约0.5秒或更长，其中第一中间流速高于初始流速并且使含硅碳的气体以比第一中间流速高的最快流速流动，以形成渐变电介质层的富碳部分。

29. 发明申请

US20060270221A1 HEATED GAS FEEDTHROUGH FOR CVD CHAMBERS 审中-公开
标题翻译：加热气体用于CVD气泡
公开(公告)号：US20060270221A1
公开(公告)日：2006-11-30
申请号：US11459585
申请日：2006-07-24
申请人： Hichem M'Saad , Dustin Ho , Juan Rocha-Alvarez
发明人： Hichem M'Saad , Dustin Ho , Juan Rocha-Alvarez
IPC分类号： H01L21/44 , C23C16/00 , H01L21/31
CPC分类号： H01L21/76826 , C23C16/401 , C23C16/45523 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02362 , H01L21/31633 , H01L21/76829
摘要： A method of processing a substrate including depositing a low dielectric constant film comprising silicon, carbon, and oxygen on the substrate and depositing an oxide rich cap on the low dielectric constant film is provided. The low dielectric constant film is deposited from a gas mixture comprising an organosilicon compound and an oxidizing gas in the presence of RF power in a chamber. The RF power and a flow of the organosilicon compound and the oxidizing gas are continued in the chamber after the deposition of the low dielectric constant film at flow rates sufficient to deposit an oxide rich cap on the low dielectric constant film.
摘要翻译：提供一种处理衬底的方法，包括在衬底上沉积包含硅，碳和氧的低介电常数膜并在低介电常数膜上沉积氧化物富盖。在室内存在RF功率的情况下，从包含有机硅化合物和氧化气体的气体混合物中沉积低介电常数膜。在低介电常数薄膜以低于在低介电常数膜上沉积富含氧化物的盖子的流速下沉积后，室内继续进行RF功率和有机硅化合物和氧化气体的流动。

30. 发明申请

US20060270217A1 Integration process for fabricating stressed transistor structure 有权
公开(公告)号：US20060270217A1
公开(公告)日：2006-11-30
申请号：US11398436
申请日：2006-04-05
申请人： Mihaela Balseanu , Jia Lee , Mei-Yee Shek , Amir Al-Bayati , Li-Qun Xia , Hichem M'Saad
发明人： Mihaela Balseanu , Jia Lee , Mei-Yee Shek , Amir Al-Bayati , Li-Qun Xia , Hichem M'Saad
IPC分类号： H01L21/44
CPC分类号： H01L29/7843 , C23C16/345 , C23C16/56 , H01L21/28044 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4925 , H01L29/66545 , H01L29/66583
摘要： A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式