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21. 发明授权

US5478780A Method and apparatus for producing conductive layers or structures for VLSI circuits 失效
标题翻译：用于生产VLSI电路的导电层或结构的方法和装置
公开(公告)号：US5478780A
公开(公告)日：1995-12-26
申请号：US851245
申请日：1992-03-13
申请人： Heinrich Koerner , Helmuth Treichel , Konrad Hieber , Peter Kuecher
发明人： Heinrich Koerner , Helmuth Treichel , Konrad Hieber , Peter Kuecher
IPC分类号： H01L21/285 , H01L21/283
CPC分类号： H01L21/28512 , Y10S438/908
摘要： Methods and apparatus for producing conductive layers or structures for VLSI circuits. In a method for producing conductive layers or structures for VLSI circuits, at least two method stages are implemented in direct succession in different chambers of a high-vacuum system without interrupting the high-vacuum conditions for the semiconductor substrate. Avoiding exposure to air between the method stages produces noticeably improved layer properties and enables particularly simple and reliable multi-stage methods for producing conductive layers that promote a multi-layer wiring on the semiconductor substrate. An apparatus for implementing the method has a plurality of high-vacuum process chambers, at least one high-vacuum distributor chamber connecting the process chambers and of at least two high-vacuum supply chambers for semiconductor substrates.
摘要翻译：用于生产VLSI电路的导电层或结构的方法和装置。在用于制造用于VLSI电路的导电层或结构的方法中，至少两个方法阶段直接连续地在高真空系统的不同室中实现，而不中断半导体衬底的高真空条件。避免在方法阶段之间暴露于空气中产生明显改善的层性质，并且能够实现特别简单可靠的多级方法来产生促进半导体衬底上的多层布线的导电层。用于实施该方法的装置具有多个高真空处理室，连接处理室和至少两个用于半导体基板的高真空供应室的至少一个高真空分配器室。

22. 发明授权

US4755486A Method of producing a defined arsenic doping in silicon semiconductor substrates 失效
标题翻译：在硅半导体衬底中制造定义的砷掺杂的方法
公开(公告)号：US4755486A
公开(公告)日：1988-07-05
申请号：US108558
申请日：1987-10-15
申请人： Helmuth Treichel , Frank S. Becker
发明人： Helmuth Treichel , Frank S. Becker
IPC分类号： H01L21/225 , H01L21/316 , H01L21/385
CPC分类号： H01L21/2255 , H01L21/31604
摘要： A method of producing a defined arsenic doping in silicon semiconductor substrates is provided. Preferably, the arsenic doping is produced in the sidewalls and floors of trenches having high aspect ratio which are etched into the substrates. An arseno-silicate glass layer is deposited into these trenches to be used as a diffusion source, the glass layer being removed after the diffusion. The arseno-silicate glass layer is deposited by thermal decomposition from the vapor phase of tetraethylortho silicate Si)OC.sub.2 H.sub.5).sub.4 and triethylarsenate AsO(OC.sub.2 H.sub.5).sub.3. A steep and reproducible doping profile having constant, maximum penetration depth and high arsenic concentration in the substrate surface which is needed for VLSI semiconductor circuits is obtained through the process of the present invention.
摘要翻译：提供了一种在硅半导体衬底中制造规定的砷掺杂的方法。优选地，在具有高纵横比的沟槽的侧壁和底板中产生砷掺杂，其被蚀刻到衬底中。在这些沟槽中沉积砷硅酸盐玻璃层作为扩散源，在扩散后去除玻璃层。通过从四乙基硅酸盐Si）OC 2 H 5）4和二乙基砷酸盐AsO（OC2H5）3的气相中的热分解沉积砷硅酸盐玻璃层。通过本发明的方法获得了在VLSI半导体电路所需的衬底表面中具有恒定的最大穿透深度和高砷浓度的陡峭且可再现的掺杂分布。

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