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21. 发明申请

US20100039142A1 INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS 有权
标题翻译：半导体器件的输入缓冲电路
公开(公告)号：US20100039142A1
公开(公告)日：2010-02-18
申请号：US12540496
申请日：2009-08-13
申请人： JI WANG LEE , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Jae Min Jang , Chang Kun Park
发明人： JI WANG LEE , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Jae Min Jang , Chang Kun Park
IPC分类号： H03K5/153
CPC分类号： H03K5/153
摘要： The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
摘要翻译：半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

22. 发明申请

US20100039140A1 BUFFER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器的缓冲电路
公开(公告)号：US20100039140A1
公开(公告)日：2010-02-18
申请号：US12494757
申请日：2009-06-30
申请人： Ji Wang Lee , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Jae Min Jang , Chang Kun Park
发明人： Ji Wang Lee , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Jae Min Jang , Chang Kun Park
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.
摘要翻译：半导体存储装置的缓冲电路包括：缓冲部，被配置为通过将输入信号的电压电平与参考电压的电压电平进行比较来增大或减小输出节点的电压电平。当参考电压的电平低于目标电平时，电压补偿部分与输出节点成比例地与参考电压的变化成比例。

23. 发明申请

US20090231006A1 DUTY CYCLE CORRECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME 有权
标题翻译：占空比校正电路和半导体集成电路设备，包括它们
公开(公告)号：US20090231006A1
公开(公告)日：2009-09-17
申请号：US12331294
申请日：2008-12-09
申请人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
发明人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K5/151 , H03K2005/00058
摘要： A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.
摘要翻译：占空比校正电路包括：相位分离器，被配置为控制DLL时钟信号的相位以产生上升时钟信号和下降时钟信号;时钟延迟单元，被配置为响应于时钟信号延迟上升时钟信号和下降时钟信号控制信号以产生延迟的上升时钟信号和延迟的下降时钟信号，占空比校正单元，被配置为产生校正上升时钟信号和校正下降时钟信号，该时钟信号响应于延迟的上升时钟信号的边沿定时而触发，延迟下降时钟信号，以及延迟控制单元，被配置为检测校正上升时钟信号和校正下降时钟信号的占空比，以产生控制信号。

24. 发明申请

US20090149142A1 RECEIVER CIRCUIT 有权
标题翻译：接收电路
公开(公告)号：US20090149142A1
公开(公告)日：2009-06-11
申请号：US12179486
申请日：2008-07-24
申请人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
发明人： Tae Jin Hwang , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee , Jae Min Jang
IPC分类号： G06F3/033
CPC分类号： G06F13/4072
摘要： A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.
摘要翻译：接收机电路能够改善其操作特性。接收器电路包括可变转换器，其被配置为在第一操作模式中在第一输出范围中输出偏移控制电压，并且根据测试模式激活信号在第二操作模式中将偏移控制电压输出到第二输出范围以及感测放大器，被配置为基于灵敏度来感测输入数据，其中灵敏度由偏移控制电压控制。

25. 发明申请

US20090128192A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME 失效
标题翻译：半导体集成电路的数据接收器及其控制方法
公开(公告)号：US20090128192A1
公开(公告)日：2009-05-21
申请号：US12176215
申请日：2008-07-18
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： G11C7/00 , H03K19/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver of a semiconductor integrated circuit includes an amplifier that outputs an amplified signal by detecting and amplifying received data using equalization function according to feedback data, a detecting unit that detects a period when data is not received in the amplifier and outputs a detecting signal, and an equalization function control unit that stops the equalization function of the amplifier in response to the detecting signal.
摘要翻译：半导体集成电路的数据接收器包括：放大器，其通过根据反馈数据使用均衡功能检测和放大接收数据来输出放大信号;检测单元，其检测在放大器中未接收到数据的周期，并输出检测信号以及均衡功能控制单元，其响应于检测信号停止放大器的均衡功能。

26. 发明申请

US20090121757A1 DATA CENTER TRACKING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME 有权
标题翻译：数据中心跟踪电路和半导体集成电路，包括它们
公开(公告)号：US20090121757A1
公开(公告)日：2009-05-14
申请号：US12174579
申请日：2008-07-16
申请人： Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L7/07
CPC分类号： H03L7/0812 , H03L7/093 , H04L7/033
摘要： A data center tracking circuit includes a clock tree, a sensing block, and a delay compensation block. The clock tree includes a plurality of clock buffers connected in series, buffers a clock, and outputs an output signal. The sensing block senses the phase change of the output signal on the basis of the clock, and outputs a sensing signal. The delay compensation block adjusts current to be supplied to the clock tree in response to the sensing signal, and adjusts the phase of the output signal.
摘要翻译：数据中心跟踪电路包括时钟树，感测块和延迟补偿块。时钟树包括串联连接的多个时钟缓冲器，缓冲时钟，并输出输出信号。感测块基于时钟感测输出信号的相位变化，并输出感测信号。延迟补偿块响应于感测信号调整提供给时钟树的电流，并调整输出信号的相位。

27. 发明授权

US08045647B2 Low power, high speed receiver circuit for use in a semiconductor integrated circuit 失效
标题翻译：用于半导体集成电路的低功率，高速接收电路
公开(公告)号：US08045647B2
公开(公告)日：2011-10-25
申请号：US12170254
申请日：2008-07-09
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： G11C7/1051 , G11C7/062 , G11C7/1069 , G11C11/56 , G11C27/026 , G11C2211/5634 , G11C2211/5642 , H04L25/0272 , H04L25/061 , H04L25/4919
摘要： A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.
摘要翻译：根据本发明的接收机电路包括与第一时钟同步的第一相位传输单元，根据多个检测电平检测输入数据，并发送第一输出信号;第一放电控制单元，其控制第二相位传输单元，响应于第一输出信号，并且通过改变确定第二相位传输的输出的节点电位来调整第二相位传输单元的传输速度，并且与第二时钟同步的第二相位传输单元检测所述输入数据根据所述第一放电控制单元的输出，并发送第二输出信号。

28. 发明申请

US20090128214A1 DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路的数据接收器
公开(公告)号：US20090128214A1
公开(公告)日：2009-05-21
申请号：US12177023
申请日：2008-07-21
申请人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Hyung Soo Kim , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03L5/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087
摘要： A data receiver includes a plurality of amplifiers for receiving data in response to clock signals having a predetermined phase difference, and amplifying the received data by performing an equalization function based on feedback data, thereby outputting amplification signals, and a plurality of latches for latching output of the amplifiers, respectively. One amplifier receives the amplification signal, as feedback data, from another amplifier receiving a clock signal having a phase more advanced than a phase of a clock signal received in the one amplifier.
摘要翻译：数据接收机包括响应于具有预定相位差的时钟信号而接收数据的多个放大器，并且通过基于反馈数据执行均衡功能来放大接收数据，从而输出放大信号，以及多个锁存器用于锁存输出的放大器。一个放大器接收作为反馈数据的放大信号，来自另一个放大器接收时钟信号，该时钟信号的相位比在一个放大器中接收的时钟信号的相位更先进。

29. 发明申请

US20090116596A1 LOW POWER, HIGH SPEED RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：低功率，高速接收电路，用于半导体集成电路
公开(公告)号：US20090116596A1
公开(公告)日：2009-05-07
申请号：US12170254
申请日：2008-07-09
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H04L7/00
CPC分类号： G11C7/1051 , G11C7/062 , G11C7/1069 , G11C11/56 , G11C27/026 , G11C2211/5634 , G11C2211/5642 , H04L25/0272 , H04L25/061 , H04L25/4919
摘要： A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.
摘要翻译：根据本发明的接收机电路包括与第一时钟同步的第一相位传输单元，根据多个检测电平检测输入数据，并发送第一输出信号;第一放电控制单元，其控制第二相位传输单元，响应于第一输出信号，并且通过改变确定第二相位传输的输出的节点电位来调整第二相位传输单元的传输速度，并且与第二时钟同步的第二相位传输单元检测所述输入数据根据所述第一放电控制单元的输出，并发送第二输出信号。

30. 发明申请

US20090059703A1 RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器接收器电路
公开(公告)号：US20090059703A1
公开(公告)日：2009-03-05
申请号：US12172108
申请日：2008-07-11
申请人： Tae Jin Hwang , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee
发明人： Tae Jin Hwang , Yong Ju Kim , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Hae Rang Choi , Ji Wang Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222
摘要： A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals.
摘要翻译：本文描述了一种接收器电路，包括：第一数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，并产生第一和第二感测信号，并响应于第一和第二感测信号产生第一内部数据第一偏移控制单元，被配置为响应于第一和第二感测信号产生第一和第二偏移信号，第一和第二偏移信号在基于第一代码确定的最大电压电平和最小电压电平之间摆动，第二偏移控制单元数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，以产生第三和第四感测信号，并响应于第三和第四感测信号产生第二内部数据; 以及第二偏移控制单元，用于响应于第三和第四感测信号产生第三和第四偏移信号，第三和第四偏移信号在基于第二代码确定的最大电压电平和最小电压电平之间摆动，其中第一和第二偏移信号数据确定单元被配置为响应于第三和第四偏移信号来确定第一内部数据的建立时间和保持时间，并且其中第二数据确定单元被配置为响应于确定第二内部数据的建立时间和保持时间到第一和第二偏移信号。

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