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21. 发明申请

US20140027706A1 SWITCHING DEVICE AND OPERATING METHOD FOR THE SAME AND MEMORY ARRAY 有权
标题翻译：切换设备及其操作方法和存储器阵列
公开(公告)号：US20140027706A1
公开(公告)日：2014-01-30
申请号：US13561558
申请日：2012-07-30
申请人： Wei-Chih Chien , Feng-Ming Lee , Ming-Hsiu Lee
发明人： Wei-Chih Chien , Feng-Ming Lee , Ming-Hsiu Lee
IPC分类号： H01L27/24 , H03K17/975
CPC分类号： G11C13/0002 , G11C13/003 , H01L27/2409 , H01L43/02 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
摘要： A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.
摘要翻译：提供了一种切换装置及其操作方法及其存储器阵列。开关装置包括第一固体电解质，第二固体电解质和开关层。开关层与第一固体电解质和第二固体电解质相邻。

22. 发明授权

US08537609B2 Memory device and method of operating the same 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US08537609B2
公开(公告)日：2013-09-17
申请号：US13161129
申请日：2011-06-15
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C8/10 , G11C11/005 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0073
摘要： A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.
摘要翻译：提供存储器件。存储器件包括存储器阵列; 电连接到存储器阵列的第一电路，并使存储器阵列以第一模式工作; 以及电连接到存储器阵列的第二电路，并且使存储器阵列以第二模式工作。

23. 发明申请

US20130153846A1 THREE DIMENSIONAL MEMORY ARRAY ADJACENT TO TRENCH SIDEWALLS 有权
标题翻译：三维尺寸记忆阵列
公开(公告)号：US20130153846A1
公开(公告)日：2013-06-20
申请号：US13330525
申请日：2011-12-19
申请人： Wei-Chih CHIEN , Ming-Hsiu Lee , Shih-Hung Chen
发明人： Wei-Chih CHIEN , Ming-Hsiu Lee , Shih-Hung Chen
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1633
摘要： A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.
摘要翻译：一种自对准堆叠式存储单元阵列结构及其制造方法。存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

24. 发明申请

US20130026516A1 LIGHT-EMITTING DIODE (LED) PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF 审中-公开
标题翻译：发光二极管（LED）包装结构及其包装方法
公开(公告)号：US20130026516A1
公开(公告)日：2013-01-31
申请号：US13223479
申请日：2011-09-01
申请人： Jih-Fu Wang , Chien-Ping Huang , Wen-Hao Lee , Hsien-Wen Chen , Ming-Hsiu Lee
发明人： Jih-Fu Wang , Chien-Ping Huang , Wen-Hao Lee , Hsien-Wen Chen , Ming-Hsiu Lee
IPC分类号： H01L33/60
CPC分类号： H01L33/486 , H01L33/62 , H01L2224/48091 , H01L2933/0033 , H01L2924/00014
摘要： A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield.
摘要翻译：提供一种发光二极管（LED）封装结构及其封装方法。封装方法包括：在硅衬底上形成第一导电层，并从硅衬底的顶表面形成反射腔和电极通孔; 在所述反射腔的表面的规定区域上形成反射层，在所述电极通孔的表面形成第二导电层和金属层; 并安装芯片并形成密封剂，以制造LED封装结构。在本发明中，不需要在电极通孔中进行用于连接硅基板的上下导电层的至少两个电镀工艺，并且导电层在电极通孔中的连接不良的问题可以是避免了，从而使制造工艺简化和时间有效，并且还提高了总产量。

25. 发明授权

US08238149B2 Methods and apparatus for reducing defect bits in phase change memory 有权
标题翻译：用于减少相变存储器中缺陷位的方法和装置
公开(公告)号：US08238149B2
公开(公告)日：2012-08-07
申请号：US12715802
申请日：2010-03-02
申请人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

26. 发明授权

US08077506B2 Method for programming a multilevel phase change memory device 有权
公开(公告)号：US08077506B2
公开(公告)日：2011-12-13
申请号：US12969526
申请日：2010-12-15
申请人： Ming-Hsiu Lee , Yi-Chou Chen
发明人： Ming-Hsiu Lee , Yi-Chou Chen
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C2013/0092
摘要： A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

27. 发明授权

US08064247B2 Rewritable memory device based on segregation/re-absorption 有权
标题翻译：基于分离/再吸收的可重写存储器件
公开(公告)号：US08064247B2
公开(公告)日：2011-11-22
申请号：US12488795
申请日：2009-06-22
申请人： Ming-Hsiu Lee , Chieh-Fang Chen , Yen-Hao Shih , Yu Zhu
发明人： Ming-Hsiu Lee , Chieh-Fang Chen , Yen-Hao Shih , Yu Zhu
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0071 , G11C2013/009 , G11C2013/0092 , G11C2213/33 , G11C2213/79 , H01L45/08 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the memory material to establish a low resistance state. The physical mechanism of programming and erasing includes movement of structure vacancies to form voids, and/or segregation of doping material and bulk material, to create the electrically insulating layer consisting of voids and/or dielectric doping material along an inter-electrode current path between electrodes.
摘要翻译：通过将电绝缘层从存储材料中物理分离出来以建立高电阻状态，并且通过将电绝缘层的至少一部分再吸收到存储材料中以建立低电阻状态。编程和擦除的物理机制包括结构空位的移动以形成空隙，和/或掺杂材料和体材料的偏析，以产生由空隙和/或介电掺杂材料构成的电绝缘层，沿着电极间电流通路电极。

28. 发明授权

US07944740B2 Multi-level cell programming of PCM by varying the reset amplitude 失效
标题翻译：通过改变复位幅度对PCM进行多级单元编程
公开(公告)号：US07944740B2
公开(公告)日：2011-05-17
申请号：US12564904
申请日：2009-09-22
申请人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
发明人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.
摘要翻译：相变存储器件及其编程方法。该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。该方法包括确定用于相变存储器件的特征化的RESET电流斜率。该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

29. 发明授权

US07869270B2 Set algorithm for phase change memory cell 有权
标题翻译：相变存储单元的集合算法
公开(公告)号：US07869270B2
公开(公告)日：2011-01-11
申请号：US12345384
申请日：2008-12-29
申请人： Ming-Hsiu Lee
发明人： Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/0038 , G11C13/0004 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2013/0092 , G11C2213/79
摘要： Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.
摘要翻译：这里描述了用于操作这样的设备的存储器件和方法。本文描述了一种用于操作包括相变材料并且可编程为包括高电阻状态和较低电阻状态的多个电阻状态的存储单元的方法。该方法包括将第一偏置装置施加到存储器单元以建立较低电阻状态，第一偏置装置包括第一电压脉冲。该方法还包括确定存储器单元是处于较低电阻状态，以及如果存储单元不处于较低电阻状态，则向存储单元施加第二偏置布置。第二偏置装置包括具有大于第一电压脉冲的脉冲高度的第二电压脉冲。

30. 发明申请

US20100221851A1 TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING 有权
标题翻译：用于检测半导体加工过程中充电效应的测试结构和方法
公开(公告)号：US20100221851A1
公开(公告)日：2010-09-02
申请号：US12777858
申请日：2010-05-11
申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
摘要翻译：半导体工艺测试结构包括电极，电荷俘获层和扩散区域。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

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