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21. 发明专利

DE3722099A1 未知
公开(公告)号：DE3722099A1
公开(公告)日：1988-01-28
申请号：DE3722099
申请日：1987-07-03
申请人： HITACHI LTD
发明人： OMAE TSUTOMU , MATSUDA TOSHIHIKO , SUKEGAWA TAKASHI , TOBISE MASAHIRO
IPC分类号： H02P7/06 , H02P25/098 , H02P29/00 , H02P5/00 , H02P5/06 , H02P5/34
摘要： A speed control apparatus for a motor comprising a motor model formed of a motor current model and a motor speed model connected in cascade, a basic torque instruction signal being applied to the motor model, and first and second control loops comparing output signals from the motor current model and the motor speed model with an instantaneous actual motor current signal and an instantaneous actual motor speed signal respectively and generating first and second correction signal to be added to the basic torque instruction signal to form a corrected torque instruction signal which is applied to a motor current control circuit, whereby a speed oscillation is suppressed even when the motor is driving an oscillatory load.

22. 发明专利

GB2190754A LOAD CURRENT DETECTING DEVICE FOR PULSE WIDTH MODULATION INVERTER 未知
公开(公告)号：GB2190754A
公开(公告)日：1987-11-25
申请号：GB8708251
申请日：1987-04-07
申请人： HITACHI LTD
发明人： HANEI HIROYUKI , HANADA TAKESHI , KUBO KENJI , WATANABE MASAHIKO , OMAE TSUTOMU , MATSUDA TOSHIHIKO
IPC分类号： H02M7/5387 , G01R19/00 , H02M7/539
摘要： A PWM inverter includes a plurality of arms connected in parallel with a d.c. power source. Each arm is constituted by an upper arm and a lower arm each having a switching element. A plurality of switching control signals are continuously and alternately applied to one and the other of the two switching elements constituting the same arm respectively. In the PWM inverter, shunt resistors are connected between a minus terminal of the d.c. power source and the lower arms respectively. The PWM inverter further comprises a waveform command generating circuit generating commands representative of current waveforms to be supplied to a load, a carrier wave generating circuit and sample-hold circuits. Each of the sample-hold circuits samples and holds a terminal voltage of the associated shunt resistor in synchronism with the period of the carrier wave generated from the carrier wave generating circuit and at specific timing in a conduction period of the associated switching element.

23. 发明专利

DE3700689A1 未知
公开(公告)号：DE3700689A1
公开(公告)日：1987-07-16
申请号：DE3700689
申请日：1987-01-12
申请人： HITACHI LTD
发明人： OMAE TSUTOMU , MATSUDA TOSHIHIKO , MIYAHARA YOUJIROU , KAMIYAMA KENZO
IPC分类号： G01P3/489 , G01P3/42 , G01P13/04 , G01P3/481
摘要： In a speed detecting apparatus for detecting the rotational speed of a rotating body mechanically coupled thereto, an encoder generates one cycle of a sine-wave signal each time its angular position of rotation changes by a predetermined unit amount. A zero-crossing pulse is generated at each zero-crossing point of the sine-wave signal generated from the encoder, and the phase angle of the sine-wave signal is detected on the basis of the zero-crossing point of the sine-wave signal generated from the encoder. In a high speed range, the rotational speed is detected on the basis of the ratio between the number of zero-crossing pulses and the time interval between a first one and a last one of the plural zero-crossing pulses. On the other hand, in a low speed range, the rotational speed is detected on the basis of the combination of the number of the zero-crossing pulses appearing within a predetermined period of time and the phase angle of the sine-wave signal.

24. 发明专利

JP2009219171A Thyristor protector 审中-公开
标题翻译：保护器
公开(公告)号：JP2009219171A
公开(公告)日：2009-09-24
申请号：JP2008056911
申请日：2008-03-06
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MATSUDA TOSHIHIKO , SATO KATSUO , YAMAZAKI AKIMITSU , YAMASHITA KEIICHI
IPC分类号： H02M1/06 , H02H7/12
摘要： PROBLEM TO BE SOLVED: To make a protection by detecting the overvoltage protective ignition of a Vbo free thyristor.
SOLUTION: Vbo free thyristors 1a-1n are given gate pulses 7 from a gate pulse generating circuit 3, at the same time, through supply paths 31a-31n. Forward voltage detecting circuits 4a-4n are connected in parallel with these thyristors 1a-1n and snubber circuits 2a-2n. The forward voltage detection signals from these forward voltage detecting circuits 4a-4n are transmitted to Vbo detecting circuits 6a-6n via, for examples, optical fibers 5a-5n. The Vbo detecting circuits 6a-6n detect breakover voltage (Vbo) of the thyristors 1a-1n, by using the gate pulses 7 and the forward voltage detecting signals, and output Vbo detection signals 8a-8n. Then, the gate pulse generating circuit 3 carries out treatment, such as, to immediately stop the output of the gate pulses 7, when the Vbo detection signals 8a-8n occurs, even from a single point of the thyristors 1a-1n.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过检测Vbo自由晶闸管的过电压保护点火来进行保护。解决方案：通过供电通路31a-31n，从栅极脉冲发生电路3向Vbo自由晶闸管1a-1n施加栅极脉冲7。正向电压检测电路4a-4n与这些晶闸管1a-1n和缓冲电路2a-2n并联连接。来自这些正向电压检测电路4a-4n的正向电压检测信号例如通过光纤5a-5n被发送到Vbo检测电路6a-6n。 Vbo检测电路6a-6n通过使用栅极脉冲7和正向电压检测信号以及输出Vbo检测信号8a-8n来检测晶闸管1a-1n的分解电压（Vbo）。然后，即使从晶闸管1a-1n的一个点起，当Vbo检测信号8a-8n发生时，门脉冲发生电路3也执行诸如立即停止栅极脉冲7的输出的处理。版权所有（C）2009，JPO＆INPIT

25. 发明专利

JP2009165348A Power converter and its abnormality detecting method 有权
标题翻译：电力变换器及其异常检测方法
公开(公告)号：JP2009165348A
公开(公告)日：2009-07-23
申请号：JP2009089540
申请日：2009-04-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MATSUDA TOSHIHIKO , KOBAYASHI KIYOTAKA , SHIGYO MASAKANE
IPC分类号： H02M1/00 , H02M1/08 , H03K17/08 , H03K17/56
摘要： PROBLEM TO BE SOLVED: To protect a power converter constituted of a plurality of IGBT elements by detecting abnormality of a gate driving circuit and abnormality of the IGBT elements certainly.
SOLUTION: The power converter is comprised of a control circuit 100, a pulse generating circuit 200 to generate a command pulse to each IGBT, a plurality of gate driving circuits 400a to 400n to conduct ON-OFF operation control of the IGBT according to the input command pulse, the IGBTs 500a to 500n to be connected to each gate driving circuit, and an abnormality detecting circuit 300. The abnormality detecting circuit judges a conflict between the command pulses RPa to RPn and gate feedback signals FBPa to FBPn output from the gate driving circuits. In case that a conflict state has continued for a given time, the circuit judges it abnormal and outputs a signal SUP to switch off all command pulses to the pulse generating circuit.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过检测栅极驱动电路的异常和IGBT元件的异常来保护由多个IGBT元件构成的功率转换器。解决方案：功率转换器由控制电路100，产生每个IGBT的指令脉冲的脉冲产生电路200，多个栅极驱动电路400a至400n根据IGBT的导通/关断操作控制输入指令脉冲，要连接到每个栅极驱动电路的IGBT 500a至500n以及异常检测电路300.异常检测电路判断指令脉冲RPa至RPn之间的冲突以及从...输出的栅极反馈信号FBPa至FBPn 门驱动电路。在冲突状态持续给定时间的情况下，电路判断为异常并且输出信号SUP以将所有命令脉冲切断到脉冲发生电路。版权所有（C）2009，JPO＆INPIT

26. 发明专利

JP2002374683A Power converter 有权
标题翻译：电源转换器
公开(公告)号：JP2002374683A
公开(公告)日：2002-12-26
申请号：JP2001180988
申请日：2001-06-15
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAGATA KOICHIRO , OKUYAMA TOSHIAKI , OKAMATSU SHIGETOSHI , MATSUDA TOSHIHIKO
IPC分类号： H02M7/48 , H02M7/483 , H02P27/06 , H02P27/08 , H02P7/63
摘要： PROBLEM TO BE SOLVED: To reduce the switching frequency of a converter of a power converter, to rapidly respond to a change, such as a disturbance or the like, and to suppress the disturbance. SOLUTION: The power converter comprises the converter for converting a DC into an AC, and an output voltage controller for comparing a voltage command value with a carrier signal and PWM-controlling an output voltage of the converter. The power converter converts the shape of the output voltage from a pulse width controlled pulse voltage into a pulse voltage to increase monotonically, until the output voltage reaches the maximum and into a pulse voltage which decreases monotonically, until the output voltage reaches the minimum in response to an operating state of the power converter.
摘要翻译：要解决的问题：为了降低功率转换器的转换器的开关频率，能够快速响应诸如干扰等的变化，并且抑制干扰。解决方案：电力转换器包括用于将DC转换成AC的转换器，以及输出电压控制器，用于将电压指令值与载波信号进行比较，并PWM控制转换器的输出电压。功率转换器将输出电压的形状从脉冲宽度控制的脉冲电压转换为脉冲电压以单调增加，直到输出电压达到最大值并且变为单调减小的脉冲电压，直到输出电压达到最小响应到电源转换器的工作状态。

27. 发明专利

JPH07219689A PRINTER AND SYSTEM USED THEREFOR 失效
公开(公告)号：JPH07219689A
公开(公告)日：1995-08-18
申请号：JP950494
申请日：1994-01-31
申请人： HITACHI LTD
发明人： MACHIDA TETSUO , MATSUDA TOSHIHIKO , KAWAOKA AKIHIRO , KAJIURA TOSHINORI
IPC分类号： G06F3/00 , G06F3/12 , G06F15/02 , B41J5/30
摘要： PURPOSE:To enable a computer to function as a printer built-in type by mounting a connection interface for the computer, and a printing means and its control means on a specific card. CONSTITUTION:A printer body 10 mounted on a type II or type 3 card of version 4.1 of the Japan Electronic Industry Development Association is inserted into the dedicated card slot 2 of the computer and electrically connected to the computer through a connector 13. At this time, a mechanism control part 108 in the printer body 10 receives a request from the computer, reads data out of an input buffer 102, and converts them into data in print format and stores the data in an output buffer 104. Further, the mechanism control part 108 reads the data out of the output buffer 104 in printing order and sends an indication to a printing head 105 to print them on a form 11, and a form driving controller 107 sends a necessary indication to a form driving part 106 to paper feed.

28. 发明专利

JPH05127710A PROGRAMMABLE CONTROLLER AND SEQUENCE CONTROL METHOD 失效
公开(公告)号：JPH05127710A
公开(公告)日：1993-05-25
申请号：JP27744791
申请日：1991-10-24
申请人： HITACHI LTD
发明人： KOBAYASHI MITSUAKI , MATSUDA TOSHIHIKO , MOROOKA YASUO , ONUMA KUNIHIKO , AZUSAZAWA NOBORU , KIKUCHI HIROMITSU
IPC分类号： G05B19/05 , G06F9/318 , G06F9/38
摘要： PURPOSE:To provide the programmable controller(PC) which processes the word operation of bit and word mixed instructions at a high speed by a general use MPU. CONSTITUTION:This programmable controller is provided with an SPU 1 which executes bit arithmetic instructions, the MPU 2 which executes word arithmetic instructions, a memory 3 for bit arithmetic which is stored with both bit and word mixed arithmetic instructions in the order of execution, and a memory 4 for word arithmetic which is stored with the object of the word arithmetic instructions in the order of execution. Further, the SPU 1 is provided with a switching means 11 (CIR) which passes a start instruction to the MPU in a stop state once recognizing the word arithmetic instruction during its execution and the MPU 2 is provided with a prefetching means 12 which fetches a next instruction during its execution. Thus, the CIR is used as the switching means to greatly reduce the overhead required for bit/word arithmetic switching and also stop the MPU in bit arithmetic, so a prefetch type can be employed as the MPU and the PC which performs high-speed processing is provided.

29. 发明专利

JPH04195416A COORDINATE INPUT DEVICE 失效
公开(公告)号：JPH04195416A
公开(公告)日：1992-07-15
申请号：JP32296590
申请日：1990-11-28
申请人： HITACHI LTD
发明人： MOURI KANEO , KANO MITSUNARI , MATSUDA TOSHIHIKO , TAKASHI MORIHIKO , KINO JIRO , KONISHI YOSHIHARU
IPC分类号： G06F3/046 , G06F3/03
摘要： PURPOSE:To realize a large-size coordinate input device by using a magnetic wire, which is magnetized in the peripheral direction, as a coordinate detecting body and using an electromagnet, which applies an AC magnetic field, for coordinate designation. CONSTITUTION:A magnetic wire 1 magnetized in the peripheral direction is used as the coordinate detecting body. An electromagnet 2 for coordinate designation is approximated to this wire 1 to generate a pulse voltage for magnetization inversion between both ends of the magnetic wire 1 as the detecting body. That is, the voltage and the distance between the magnetic wire 1 and the electromagnet 2 for coordinate designation have certain relations, and therefore, plural magnetic wires 1 are arranged and coordinates of the electromagnet 2 for coordinate designation are calculated in accordance with detected voltages of magnetic wires 1 to realize a coordinate input device. Thus, a detection signal of high S/N is obtained, and the large-size coordinate input device is realized.

30. 发明专利

JPH04186401A METHOD AND DEVICE FOR TUNING DIGITAL CONTROL DEVICE 失效
公开(公告)号：JPH04186401A
公开(公告)日：1992-07-03
申请号：JP31383090
申请日：1990-11-21
申请人： HITACHI LTD
发明人： MATSUDA TOSHIHIKO , TOBIYO MASAHIRO , KAMIYAMA KENZO
IPC分类号： G05B13/02 , G05D13/62
摘要： PURPOSE:To attain auto-tuning without reducing a control response speed by connecting a specific control gain tuning device to a digital control device and tuning the control characteristics of the device. CONSTITUTION:A data I/O means 103 rewrites control response data stored in a control response storing means 102 and feedback control gain. A control gain tuning device 5 inputs the control response data stored in the means 102 by a control response reading means 51 through the means 103 and finds out an evaluation index by a control response evaluating means 522 based upon set control characteristics set up in a control characteristic setting means 53 and the control response data. A control gain correcting means 54 corrects the control gain based upon the evaluation index and then the means 103 corrects the corrected control gain to tune control characteristics to required ones. Thus auto-tuning can be attained without reducing the control response speed.

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