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21. 发明专利

JPH03206549A INFORMATION PROCESSOR 失效
公开(公告)号：JPH03206549A
公开(公告)日：1991-09-09
申请号：JP28423590
申请日：1990-10-24
申请人： HITACHI LTD
发明人： ASAI MITSUO , MASUDA NOBORU , YASUNAGA MORITOSHI , YAGYU MASAYOSHI , YAMADA MINORU , SHIBATA KATSUNARI
IPC分类号： G06G7/60 , G06F15/18 , G06N3/04 , G06N3/08 , G06N99/00
摘要： PURPOSE:To obtain a high speed and compact neural net of a large scale by providing a communication means between two networks which perform the forward and backward calculations respectively. CONSTITUTION:The calculation units 120F and 121F form a forward network which performs a forward operation, and the calculation units 120B and 121B form a backward network which performs a backward operation respectively. A means is added to carry out the mutual communication between both networks. Each network holds the weight value for the benefit of the parallel calculations of each network. As a result, the same weight is held double and this double holding of the same weight value is corrected by each network. The corrected results are equal to each other. Thus a high-speed neural network of a large scale is obtained in a compact size.

22. 发明专利

JPH03166743A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, INSPECTING METHOD, PREPAIRING METHOD AND USING METHOD THEREOF 失效
公开(公告)号：JPH03166743A
公开(公告)日：1991-07-18
申请号：JP30461789
申请日：1989-11-27
申请人： HITACHI LTD
发明人： YASUNAGA MORITOSHI , MASUDA NOBORU , YAGYU MASAYOSHI , ASAI MITSUO , YAMADA MINORU
IPC分类号： G01R31/28 , G06F1/30 , G06F11/22 , H01L21/66
摘要： PURPOSE:To facilitate an inspection and to inspect the entire device even if a power source trouble exists in a functional block by providing a plurality of functional blocks connected to a common power source through branch power lines, and electrically separating the block having the trouble from the common power source. CONSTITUTION:An inspecting device is connected to a signal bus. Thus, functional blocks 1 can be individually inspected by the device through the bus. Since the device is not, if once connected, necessarily disconnected until an inspection is finished, the sequential movement, alignment, contact of an inspection needle are not required, and a high speed inspection is conducted. The branch power line 5, of the block 1' in which a power source is short-circuited at 2 is disconnected at 6 thereby to return the power source voltage drop due to the short-circuit 2 to a normal voltage. Accordingly, other block having no trouble can be inspected. Thus, the inspection is facilitated, and the inspection of the function particularly when the power source trouble occurs can be facilitated.

23. 发明专利

JPH03105966A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03105966A
公开(公告)日：1991-05-02
申请号：JP24201289
申请日：1989-09-20
申请人： HITACHI LTD
发明人： ISHIBASHI KENICHI , HAYASHI TAKEHISA , DOI TOSHIO , ASAI MITSUO
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06
摘要： PURPOSE:To execute a designing operation by sufficiently utilizing a device performance and to offer a high-performance semiconductor integrated circuit device by a method wherein a load capacity driven by individual logic circuits is found on the basis of information on a layout of an LSI and a high-speed circuit is selected according to its load. CONSTITUTION:A layout operation of an LSI is executed by using a specific logic circuit cell out of a second BiCMOS circuit and a CMOS circuit; a load capacity driven by individual logic circuits is found on the basis of its result. Then, a circuit whose delay time is minimum is selected according to the load capacity; a logic circuit cell is replaced. Thereby, it is possible to obtain a high-performance circuit device in which a first BiCMOS circuit, the second BiCMOS circuit and the CMOS circuit are mixed and which sufficiently utilizes a device performance. It is decided in advance that the first BiCMOS circuit is used as a circuit to drive an interconnection between logic blocks and that the second BiCMOS circuit is used as a circuit to drive an interconnection between logic circuits. When a layout operation is executed by this decision, it is possible to obtain the high-performance semiconductor integrated circuit device which fully utilizes the device performance.

24. 发明专利

JPH02121349A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS DESIGN 失效
公开(公告)号：JPH02121349A
公开(公告)日：1990-05-09
申请号：JP27297088
申请日：1988-10-31
申请人： HITACHI LTD
发明人： DOI TOSHIO , HAYASHI TAKEHISA , ISHIBASHI KENICHI , ASAI MITSUO
IPC分类号： H01L21/3205 , G11C11/34 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04 , H03K19/173
摘要： PURPOSE:To make it possible to design a high-speed LSI in a short time by a method wherein a potential is fixed in the upper layer of a wiring layer and moreover, there is at least one layer of a shielding layer to cover nodes in a cell and at the same time, at least one layer of a wiring layer to make an intercell connection is arranged on the upper layer of the shielding layer. CONSTITUTION:In a three-input AND cell 101 using a precharge circuit, specifications on the layout of the arrangement of a power wiring and a grounding wiring, the external shape and height of the cell, the positions of input/ output terminals and the like are set in specifications identical with those of a standard cell (an inverter cell) 102 of a CMOS static circuit. Therefore, the arrangement of the cell can be conducted using a DA technique identical with that used for the arrangement of the standard cell. Moreover, as the space over dynamic nodes 9 to 11 in the cell is covered with the power wiring VDD and the grounding wiring GND, whose potentials are fixed, an electrostatic capacity between a signal wiring i101 passing through the space over the cell and the nodes is inhibited sufficiently small. Accordingly, there is no limit to a wiring in the space over the cell. Thereby, an intercell connecting wiring can be automatized like that in the standard cell.

25. 发明专利

JP2000278637A VIDEO TRANSMISSION DEVICE 失效
公开(公告)号：JP2000278637A
公开(公告)日：2000-10-06
申请号：JP8538899
申请日：1999-03-29
申请人： HITACHI LTD
发明人： MORITA KOICHI , ASAI MITSUO , ONODERA TAKESHI , ISHIDA TOMOYUKI , TAKIYASU YOSHIHIRO
IPC分类号： H04N5/781 , G11B27/00 , H04N5/262 , H04N5/765 , H04N5/91
摘要： PROBLEM TO BE SOLVED: To perform every day change efficiently by permitting an outer unit to recognize plural files in a reproduction order that an operator desires as one continuous medium and constituting a device so that it is operated with an instruction from the outer unit as a continuous video following the order. SOLUTION: An outer unit issuing the instruction of transmission start and transmission stop to a video transmission device is permitted to recognize the plural files of a reproduction order that an operator desires as one continuous medium and the video transmission device is constituted so that it is operated with the instruction from the outer unit as a continuous video following the order. A CPU 111, a memory 106 storing a program for executing a processing by the CPU 111 and a control instruction interface 108 are connected to the video transmission device 100, for example. Then, a control computer 112 controlling the transmission of the video and a monitor 115 are connected through the control instruction interface 108.

26. 发明专利

JPH10150584A DIGITAL STUDIO EQUIPMENT AND ITS CONTROL METHOD 失效
公开(公告)号：JPH10150584A
公开(公告)日：1998-06-02
申请号：JP30772096
申请日：1996-11-19
申请人： HITACHI LTD
发明人： YAMASHITA YOJI , TAKIYASU YOSHIHIRO , ASAI MITSUO , HIROSE NOZOMI , IWANAGA YOSHIO , ONO RYUICHI , ONODERA TAKESHI
IPC分类号： H04N5/765 , H04L29/06 , H04N5/222 , H04N5/781 , H04N7/173 , H04N21/21 , H04N21/27
摘要： PROBLEM TO BE SOLVED: To provide the CSS digital studio equipment and its control method by solving a problem of performance that has not been realized by a conventional CSS in constructing a CSS digital studio system. SOLUTION: In the system, a client 100, on which a video data processing means conducting read, display or edit of video data, is mounted and one or more servers 200 having one or more secondary storage devices, such as a magnetic disk device are interconnected by a network 300. The server receives a data access request from the client, issues a data access request, returns the result of data access to the client, and receives the data access request to access the secondary storage device 250 to access to video data 400.

27. 发明专利

JPH07236132A DEVICE AND SYSTEM FOR STORING AND DISTRIBUTING VIDEO 失效
公开(公告)号：JPH07236132A
公开(公告)日：1995-09-05
申请号：JP28943694
申请日：1994-11-24
申请人： HITACHI LTD
发明人： ASAI MITSUO , TAKIYASU YOSHIHIRO , SHIBATA KOICHI , SATOU MIKIKO , SAITO ATSUSHI , HAYASHI TAKEHISA , IGAWA MASARU
IPC分类号： G06F13/00 , H04N5/765 , H04N5/781 , H04N5/783 , H04N5/85 , H04N5/926 , H04N5/93 , H04N7/10 , H04N7/173 , H04N21/231 , H04N21/2387
摘要： PURPOSE:To improve through-put, to simultaneously supply data to plural users and to guarantee the service quality QOS of a distributing channel by controlling the connection of plural video storingi/distributing devices to an information processor and a network through a switch unit. CONSTITUTION:When a video data reading request is outputted from an information processor to a video storing/distributing system 101, a control unit 190 recognizes storing addresses stored in respective video storing/distributing devices 102 to 105 based upon management information 166, and when distribution is possible as the result of referring to a QOS management table 160, connection is set up and a switch pass 140 is controlled to distribute video data. Once a certain video storing/distributing device consents to a distribution instruction from the control unit 190, the QOS of video data to be successively distributed is managed by a control block in the distributing device concerned. Consequently the picture quality of video data can be guaranteed and the video data can be simultaneously distributed to plural users.

28. 发明专利

JPH07110724A PROCESSOR 失效
公开(公告)号：JPH07110724A
公开(公告)日：1995-04-25
申请号：JP25671093
申请日：1993-10-14
申请人： HITACHI LTD
发明人： ASAI MITSUO , OKADA TETSUHIKO , SUZUKI MIKIKO , TAKEDA HIROSHI , HAYASHI TAKEHISA
IPC分类号： G06F1/04
摘要： PURPOSE:To reduce the power consumption by extending the phase of less power consumption in the power down mode where the operation frequency is reduced. CONSTITUTION:The reference clock having a frequency (f) is inputted from a clock signal input terminal 101 to generate a signal CK1A having a frequency f/2 and a signal CK2A, whose phase is delayed by a half period, by a 1/2 frequency divider 203. The signal which is obtained from the signal CK1A by a 1/2 frequency divider 204 and has 174 frequency of CK and the signal CK1A are connected to an AND circuit 207 to output a signal CK1B. A signal having 1/8 frequency of CK and a signal CK2B are connected to an AND circuit 208 to generate a signal CK1C. A power down mode set terminal 102 is set to select the signal CK1A or CK1C by a selector circuit 210, and the selected signal is sent to a non-overlap clock driver 250, and signals K1 and K2 are outputted to a clock signal output terminal 231 and an output terminal 241 respectively.

29. 发明专利

JPH06139222A NEURO COMPUTER 失效
公开(公告)号：JPH06139222A
公开(公告)日：1994-05-20
申请号：JP29244992
申请日：1992-10-30
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： OCHIAI TATSUO , SHIBATA KATSUNARI , ASAI MITSUO , SATO YUJI , SAKAGUCHI TAKAHIRO , HASHIMOTO MASA , TAKAYANAGI HIROSHI , MOGI KEIJI , OKABASHI TAKUO , KUWABARA YOSHIHIRO
IPC分类号： G06F15/16 , G06F15/177 , G06F15/18 , G06F15/80 , G06G7/60 , G06N3/06 , G06N3/10 , G06N99/00
摘要： PURPOSE:To speed up the execution of a neural network by inhibiting an in- neuron memory from being rewritten with a rewrite instruction to the memory according to the value that a specific internal signal indicates. CONSTITUTION:A data arithmetic circuit 107 performs the arithmetic operation of neurons and outputs arithmetic state signals 120-123 to a group control circuit 109. The arithmetic state signals 120-123 are processed so that group conditions are shown, and their value is written in a condition code register(CCR) 113. The output of the CCR 113 is selected by a selector 114 and group information is taken in a group flag group 115. The output of the group flag group 115 is led to an OR gate 116, whose outputs are all sent to an AND gate 118 to generate an internal memory write acknowledgment signal 128. Consequently, the arithmetic result of only a grouped neuron circuit 101 is written in an internal memory group 108.

30. 发明专利

JPH06139049A PARALLEL DATA PROCESSOR 失效
公开(公告)号：JPH06139049A
公开(公告)日：1994-05-20
申请号：JP29244392
申请日：1992-10-30
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： OKABASHI TAKUO , ASAI MITSUO , SHIBATA KATSUNARI , SATO YUJI , HASHIMOTO MASA , SAKAGUCHI TAKAHIRO , TAKAYANAGI HIROSHI , MOGI KEIJI , OCHIAI TATSUO , KUWABARA YOSHIHIRO
IPC分类号： G06F7/38 , G06F7/53 , G06F15/18 , G06G7/60 , G06N99/00
摘要： PURPOSE:To advance an arithmetic operation by an entire device without operating a processing for an overflow by returning the maximum value to be expressed without generating the overflow at the time of processing data in which more than one results of the computing element of a parallel arithmetic processing unit overflow, and advancing the arithmetic operation by using the result. CONSTITUTION:An arithmetic element is constituted of a register file 1, memory 2 which stores the weight value of a neuron, shifter 3, ALU 5, and multiplier 7. Then, when the positive overflow of the arithmetic result is generated, the arithmetic operation is continued by using the positive maximum value to be expressed by the computing element as the arithmetic result, and when negative overflow of the arithmetic result is generated, the arithmetic operation is continued by using the additional maximum value to be expressed by the computing element as the arithmetic result. An overflow circuit 6 outputs 7FFFFFFFHEX at the time of the generation of the positive overflow, and outputs 8OOOOOOOHEX at the time of the generation of the negative overflow. A rounding circuit 4 operates a rounding in a zero direction at the time of executing an arithmetic right-shift by a shifter 3.

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