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    • 29. 发明授权
    • Array substrate and method for fabricating the same
    • 阵列基板及其制造方法
    • US09548324B2
    • 2017-01-17
    • US14430310
    • 2014-05-12
    • BOE TECHNOLOGY GROUP CO., LTD.
    • Yanzhao LiGang WangDongfang WangWei LiuJingang Fang
    • H01L27/12H01L29/786H01L21/027
    • H01L27/1288H01L21/0274H01L29/786H01L2924/0002H01L2924/00
    • An array substrate and a method for fabricating the same are disclosed. The method includes steps of providing a substrate (20), a first metal layer including patterns of gate electrodes (21, 24) of a first and second TFTs, an active layer (27) and a gate insulation layer (28) are formed on the substrate; forming an etch stop layer film and a photoresist sequentially on the substrate (20), and allowing the photoresist to form a first, second and third regions through gray-scale exposing and developing; forming a pattern of an etch stop layer (29), a connection via hole (30), and a contact via hole (31) respectively in the first, second and third regions through a patterning process; and forming source electrodes and drain electrodes (22, 23,25, 26) of the first and second TFTs. Photoresist of different thicknesses are disposed according to etch depths, thereby avoiding the over-etch of relatively shallow via holes.
    • 公开了阵列基板及其制造方法。 该方法包括提供衬底(20)的步骤,包括第一和第二TFT的栅电极(21,24)的图案的第一金属层,有源层(27)和栅绝缘层(28)形成在 基材; 在衬底(20)上依次形成蚀刻停止层膜和光致抗蚀剂,并且通过灰度曝光和显影使光致抗蚀剂形成第一,第二和第三区域; 通过图案化工艺在第一,第二和第三区域分别形成蚀刻停止层(29),连接通孔(30)和接触通孔(31)的图案; 以及形成所述第一和第二TFT的源电极和漏电极(22,23,25,26)。 根据蚀刻深度设置不同厚度的光刻胶,从而避免相对浅的通孔的过度蚀刻。