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21. 发明申请

US20070194355A1 Transistor device with two planar gates and fabrication process 有权
标题翻译：具有两个平面栅极和制造工艺的晶体管器件
公开(公告)号：US20070194355A1
公开(公告)日：2007-08-23
申请号：US11698755
申请日：2007-01-26
申请人： Romain Wacquez , Philippe Coronel , Damien Lenoble , Robin Cerutti , Thomas Skotnicki
发明人： Romain Wacquez , Philippe Coronel , Damien Lenoble , Robin Cerutti , Thomas Skotnicki
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L27/1203 , H01L29/78648
摘要： A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.
摘要翻译：平面晶体管器件包括两个独立的栅极（第一和第二栅极）以及位于栅极之间的半导体沟道。半导体通道由第一材料形成。通道包括相对的端部，其包括介电区域，沟道区域位于栅极之间。介电区包括第一材料的氧化物。

22. 发明授权

US06969878B2 Surround-gate semiconductor device encapsulated in an insulating medium 有权
标题翻译：封装在绝缘介质中的环绕栅极半导体器件
公开(公告)号：US06969878B2
公开(公告)日：2005-11-29
申请号：US10409653
申请日：2003-04-08
申请人： Philippe Coronel , Stephane Monfray , Thomas Skotnicki
发明人： Philippe Coronel , Stephane Monfray , Thomas Skotnicki
IPC分类号： H01L21/336 , H01L29/786 , H01L21/84
CPC分类号： H01L29/66772 , H01L29/78648 , H01L29/78654
摘要： A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.
摘要翻译：提供一种半导体器件，其包括在半导体源极区域和半导体漏极区域之间沿纵向方向在半导体衬底上方延伸的半导体沟道区域和在横向方向上延伸的栅极区域，涂覆沟道区域并与渠道区域。源极，沟道和漏极区域形成在大致平面并平行于衬底的上表面的连续半导体层中。此外，源极，漏极和栅极区域被涂覆在绝缘涂层中，以便在栅极区域和源极和漏极区域之间以及衬底与源极，漏极，栅极和沟道区域之间提供电绝缘。还提供了一种包括这种半导体器件的集成电路及其制造方法。

23. 发明授权

US08951458B2 Producing a deformable system with a view to displacing an object enclosed in the latter 有权
标题翻译：产生可变形系统，以便移动封闭在后者中的物体
公开(公告)号：US08951458B2
公开(公告)日：2015-02-10
申请号：US13220288
申请日：2011-08-29
申请人： Mohammed Benwadih , Jacqueline Bablet , Philippe Coronel
发明人： Mohammed Benwadih , Jacqueline Bablet , Philippe Coronel
IPC分类号： B29C39/10
CPC分类号： B29C71/02 , G02B6/3512 , G02B6/3572 , G02B6/3576 , H01L51/055 , Y10T29/49002 , Y10T29/49908
摘要： The invention relates to a method for displacing an object in a solid system involving the following steps: placing the object in a matrix which is solid at a first temperature and capable of softening due to the effect of a temperature increase; if necessary, increasing the temperature until the matrix softens; applying an external action to the object so as to move it inside the matrix; lowering the temperature until the matrix solidifies.
摘要翻译：本发明涉及一种用于置换固体系统中的物体的方法，包括以下步骤：将物体放置在第一温度下为固体并且由于温度升高的影响而能够软化的矩阵中; 如果需要，增加温度直到基体软化; 对对象施加外部动作，以将其移动到矩阵内部; 降低温度直到基体凝固。

24. 发明申请

US20130256937A1 POLYMER LOCALLY COMPRISING CONDUCTIVE AREAS 有权
标题翻译：聚合物包含导电区域
公开(公告)号：US20130256937A1
公开(公告)日：2013-10-03
申请号：US13990164
申请日：2011-12-05
申请人： Gilles Philippot , Philippe Coronel , Jacqueline Bablet , Mohamed Benwadih
发明人： Gilles Philippot , Philippe Coronel , Jacqueline Bablet , Mohamed Benwadih
IPC分类号： H01B13/00
CPC分类号： H01B13/00 , H01L51/0023 , H01L51/102
摘要： A method for producing a conductive area in a polymer material comprises: providing a polymer layer comprising conductive particles with a density such that the polymer layer is insulating, heating the polymer material to a temperature higher than or equal to the glass transition temperature of the polymer material, compressing a portion of the polymer layer using a stamp, in order to obtain a density of conductive particles such that the portion becomes conductive, and removing the stamp from the polymer layer.
摘要翻译：用于在聚合物材料中制造导电区域的方法包括：提供包含导电颗粒的聚合物层，其密度使得聚合物层是绝缘的，将聚合物材料加热到高于或等于聚合物的玻璃化转变温度的温度材料，使用印模压缩聚合物层的一部分，以获得导电颗粒的密度，使得该部分变得导电，以及从聚合物层去除印模。

25. 发明授权

US08460978B2 Method for manufacturing a transistor with parallel semiconductor nanofingers 有权
标题翻译：制造具有并联半导体纳米装置的晶体管的方法
公开(公告)号：US08460978B2
公开(公告)日：2013-06-11
申请号：US12063288
申请日：2006-08-07
申请人： Philippe Coronel , Jessy Bustos , Romain Wacquez
发明人： Philippe Coronel , Jessy Bustos , Romain Wacquez
IPC分类号： H01L21/00 , H01L27/01
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66772
摘要： A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.
摘要翻译：一种制造具有并联半导体纳米装置的晶体管的方法。该方法包括：在可以相对于单晶层选择性地蚀刻的下层材料层上形成半导体材料的单晶层; 蚀刻单晶层和下层中的平行隔板，并继续进行所述蚀刻操作，以便中断部分下层材料; 用第一绝缘材料填充隔板和中空部分之间的间隙; 限定隔板的中心部分，并且从单晶层的中心部分周围去除第一绝缘材料，从而形成半导体材料的手指; 并用导体材料填充和涂覆中心部分。

26. 发明授权

US08383464B2 Method for producing field effect transistors with a back gate and semiconductor device 有权
标题翻译：用背栅极和半导体器件制造场效晶体管的方法
公开(公告)号：US08383464B2
公开(公告)日：2013-02-26
申请号：US12941562
申请日：2010-11-08
申请人： Claire Fenouillet-Beranger , Philippe Coronel
发明人： Claire Fenouillet-Beranger , Philippe Coronel
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/76283 , H01L21/764 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： The method for producing a field effect transistor on a substrate comprising a support layer, a sacrificial layer and a semi-conducting layer comprises forming an active area in the semi-conducting layer. The active area is delineated by a closed peripheral insulation pattern and comprises an additional pattern made from insulating material. The method also comprises etching the insulating material of the additional pattern to access the sacrificial layer, etching the sacrificial layer resulting in formation of a first cavity, forming a dielectric layer on a top wall of the first cavity, and depositing an electrically conducting layer in the first cavity. The closed peripheral insulation pattern is formed through the semi-conducting layer and the sacrificial layer.
摘要翻译：在包括支撑层，牺牲层和半导体层的衬底上制造场效应晶体管的方法包括在半导电层中形成有源区。有源区域由封闭的外围绝缘图案描绘并且包括由绝缘材料制成的附加图案。该方法还包括蚀刻附加图案的绝缘材料以进入牺牲层，蚀刻牺牲层，从而形成第一腔，在第一腔的顶壁上形成电介质层，并将导电层沉积在第一个腔。封闭的外围绝缘图案通过半导体层和牺牲层形成。

27. 发明申请

US20120292183A1 Stand-Alone Water Detection Device That Includes a Hydrogen Source 审中-公开
标题翻译：包含氢源的独立水检测装置
公开(公告)号：US20120292183A1
公开(公告)日：2012-11-22
申请号：US13575282
申请日：2011-01-20
申请人： Jessica Thery , Philippe Coronel , Vincent Faucheux , Jean-Yves Laurent
发明人： Jessica Thery , Philippe Coronel , Vincent Faucheux , Jean-Yves Laurent
IPC分类号： G01N27/411 , G01N27/417
CPC分类号： G01N27/4162 , H01M8/04492 , H01M8/1007
摘要： A water detection device comprising at least one fuel cell comprising a first electrode, a layer of electrolyte, a second electrode and an electrical measurement device characterized in that the first electrode of the cell is in contact with a first face of a porous silicon substrate comprising Si—H bonds, in such a manner as to liberate a flow of hydrogen in the presence of water. Advantageously, the substrate of porous silicon is incorporated into a first housing permeable to water, the fuel cell being incorporated into a second housing said second housing being impermeable to water and permeable to oxygen.
摘要翻译：一种水检测装置，包括至少一个包括第一电极，电解质层，第二电极和电测量装置的燃料电池，其特征在于，电池的第一电极与多孔硅衬底的第一面接触，包括 Si-H键，以在存在水的情况下释放出氢气流。有利地，多孔硅的基底结合到可渗透水的第一壳体中，燃料电池结合到第二壳体中，所述第二壳体不透水并且可透氧。

28. 发明授权

US08252638B2 Method for forming under a thin layer of a first material portions of another material and/or empty areas 有权
标题翻译：用于在另一材料和/或空区域的第一材料部分的薄层下形成的方法
公开(公告)号：US08252638B2
公开(公告)日：2012-08-28
申请号：US11712353
申请日：2007-02-28
申请人： Philippe Coronel , Yves Laplanche , Laurent Pain
发明人： Philippe Coronel , Yves Laplanche , Laurent Pain
IPC分类号： H01L21/84 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/0277 , H01L21/7682 , H01L29/42384 , H01L29/42392 , H01L29/78654
摘要： A method for forming an empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.
摘要翻译：一种用于在给定材料的层下形成空区域的方法，包括在基底上形成感光层和给定材料层的堆叠; 根据所述感光层是正或负的，电子束穿过所述给定材料的层，使所述感光层或其互补体的一部分粘合; 并去除感光层的一部分。

29. 发明授权

US08048751B2 Method for producing a field effect device having self-aligned electrical connections with respect to the gate electrode 有权
标题翻译：用于制造具有相对于栅电极的自对准电连接的场效应器件的方法
公开(公告)号：US08048751B2
公开(公告)日：2011-11-01
申请号：US12879572
申请日：2010-09-10
申请人： Claire Fenouillet-Béranger , Philippe Coronel
发明人： Claire Fenouillet-Béranger , Philippe Coronel
IPC分类号： H01L21/336
CPC分类号： H01L21/76895 , H01L21/76808 , H01L21/76897 , H01L29/665 , H01L29/66583
摘要： A gate dielectric, an insulating layer and an etching mask are formed on substrate. The etching mask delineates at least the gate electrode and the source and drain contacts and the source, drain and gate output lines of the first metal level of a field effect device. The gate electrode and the future source and drain contacts are formed simultaneously by etching of the insulating layer. A gate material is deposited to form the gate electrode. The source and drain contacts are formed at least in the insulating layer. The source, drain and gate output lines of the first metal level are formed in the etching mask.
摘要翻译：在基板上形成栅极电介质，绝缘层和蚀刻掩模。蚀刻掩模至少描绘了场效应器件的第一金属级的栅电极和源极漏极接触以及源极，漏极和栅极输出线。通过蚀刻绝缘层同时形成栅极电极和未来的源极和漏极触点。沉积栅极材料以形成栅电极。源极和漏极触点至少形成在绝缘层中。在蚀刻掩模中形成第一金属层的源极，漏极和栅极输出线。

30. 发明申请

US20100308411A1 METHOD FOR FORMING AN INTEGRATED CIRCUIT LEVEL BY SEQUENTIAL TRIDIMENSIONAL INTEGRATION 有权
标题翻译：通过顺序三维集成形成集成电路电平的方法
公开(公告)号：US20100308411A1
公开(公告)日：2010-12-09
申请号：US12794092
申请日：2010-06-04
申请人： Perceval Coudrain , Philippe Coronel , Nicolas Buffet
发明人： Perceval Coudrain , Philippe Coronel , Nicolas Buffet
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2924/00011 , H01L2224/80001
摘要： A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator.
摘要翻译：一种用于在其上形成部件的第一支撑件上形成三维结构水平的方法，包括以下步骤：在第二半导体支架上形成具有插入的热氧化物层的单晶半导体衬底; 将单晶半导体衬底的自由表面放置在第一支撑件的上表面上; 消除了第二个半导体支持; 并将热氧化层减薄至能够形成栅极绝缘体的厚度。

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