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21. 发明授权

US06664164B2 UV-programmed P-type Mask ROM and fabrication thereof 有权
公开(公告)号：US06664164B2
公开(公告)日：2003-12-16
申请号：US10125270
申请日：2002-04-16
申请人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
发明人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
IPC分类号： H01L218236
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792
摘要： A method for fabricating an UV-programmed P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell be in a first logic state, in which the channel is hard to switch on, in order to prevent a leakage current. After the bit lines and the word lines are formed, the Mask ROM is programmed by irradiating the substrate with UV light to inject electrons into the ONO layer under the openings to make the memory cells under the openings be in a second logic state.

22. 发明授权

US06620694B1 Method of making non volatile memory with a protective metal line 有权
标题翻译：用保护金属线制造非易失性存储器的方法
公开(公告)号：US06620694B1
公开(公告)日：2003-09-16
申请号：US10128716
申请日：2002-04-23
申请人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
发明人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L21/28282 , H01L21/743 , H01L21/76892 , H01L27/115 , H01L29/66833
摘要： A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate. In addition, there is a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via different contacts, respectively. The protective metal line has a resistance higher than that of the word-line.
摘要翻译：描述非易失性存储器及其制造。非易失性存储器包括衬底上的字线，字线和衬底之间的电荷俘获层，以及与衬底上的字线电连接的触点。此外，存在与字线电连接的保护金属线和分别经由不同触点的衬底中的接地掺杂区域。保护金属线的电阻比字线高。

23. 发明授权

US06444519B1 Method for forming a capacitor in a mixed mode circuit device by ion implantation 有权
标题翻译：通过离子注入在混合模式电路器件中形成电容器的方法
公开(公告)号：US06444519B1
公开(公告)日：2002-09-03
申请号：US10120286
申请日：2002-04-09
申请人： Chien-Hung Liu , Shou-Wei Huang , Shyi-Shuh Pan
发明人： Chien-Hung Liu , Shou-Wei Huang , Shyi-Shuh Pan
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/26533 , H01L21/32105
摘要： The invention provides a method for forming a capacitor in a mixed mode circuit device through ion implantation. The method includes forming a polysilicon layer over a substrate, which substrate has isolation region formed thereon. An ion implantation process is performed to implant oxygen ions into the polysilicon layer. An annealing process is performed to trigger an reaction between the oxygen ions and the silicon ions. As a result, a silicon oxide layer is formed within the polysilicon layer. The silicon layer and the polysilicon layer are patterned, where the top portion of the polysilicon layer above the silicon oxide layer serves as an upper electrode of a capacitor. The polysilicon layer below the silicon oxide layer serves as the lower electrode.
摘要翻译：本发明提供了一种通过离子注入在混合模式电路器件中形成电容器的方法。该方法包括在衬底上形成多晶硅层，该衬底上形成有隔离区。执行离子注入工艺以将氧离子注入到多晶硅层中。执行退火处理以触发氧离子和硅离子之间的反应。结果，在多晶硅层内形成氧化硅层。图案化硅层和多晶硅层，其中氧化硅层上方的多晶硅层的顶部用作电容器的上电极。氧化硅层下面的多晶硅层用作下电极。

24. 发明授权

US06876044B2 UV-programmable P-type mask ROM 有权
标题翻译： UV可编程P型掩模ROM
公开(公告)号：US06876044B2
公开(公告)日：2005-04-05
申请号：US10680023
申请日：2003-10-06
申请人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
发明人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
IPC分类号： H01L21/8246 , H01L27/115 , H01L29/792 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792
摘要： An ultraviolet-programmable P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell to be in a first logic state, in which the channel is hard to switch on, in order to prevent a leakage current. After the bit lines and the word lines are formed, the Mask ROM is programmed by irradiating the substrate with UV light to inject electrons into the ONO layer under the openings to make the memory cells under the openings be in a second logic state.
摘要翻译：描述了紫外线可编程P型掩模ROM。首先提高所有存储器单元的阈值电压，以使每个存储器单元处于通道难以接通的第一逻辑状态，以防止漏电流。在形成位线和字线之后，通过用UV光照射衬底来编程掩模ROM，以将电子注入到开口下面的ONO层中，以使开口下的存储单元处于第二逻辑状态。

25. 发明授权

US06812507B2 Non-volatile memory capable of preventing antenna effect and fabrication thereof 有权
标题翻译：能够防止天线效应和制造的非易失性存储器
公开(公告)号：US06812507B2
公开(公告)日：2004-11-02
申请号：US10636448
申请日：2003-08-06
申请人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
发明人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
IPC分类号： H01L27148
CPC分类号： H01L29/66833 , H01L21/28282 , Y10S438/954
摘要： A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.
摘要翻译：描述能够防止天线效应及其制造的非易失性存储器。非易失性存储器包括在基板上具有高电阻部分和存储单元部分的字线以及位于字线和基板之间的电荷捕获层。高电阻部分与衬底中的接地掺杂区域电连接，并且存储单元部分与衬底上的金属互连电连接。

26. 发明授权

US06723603B2 Method of utilizing fabrication process of poly-Si spacer to build flash memory with 2bit/cell 有权
标题翻译：利用多硅衬垫制造工艺构建2bit / cell的闪速存储器的方法
公开(公告)号：US06723603B2
公开(公告)日：2004-04-20
申请号：US10183530
申请日：2002-06-28
申请人： Chien-Hung Liu , Erh-Kun Lai , Shyi Shuh Pan , Shou Wei Huang , Ying Tzoo Chen
发明人： Chien-Hung Liu , Erh-Kun Lai , Shyi Shuh Pan , Shou Wei Huang , Ying Tzoo Chen
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7887
摘要： The present invention provides a method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2bit/cell. In the present invention, recessed poly-Si spacers are used to fabricate discontinuous floating gates below a control gate to build a flash memory with 2bit/cell. The present invention is characterized in that the fabrication process of poly-Si spacers is exploited to complete the fabrication process of floating gates in automatic alignment way without any extra mask process. Moreover, each memory cell in this flash memory can store two bits, hence increasing the memory capacity.
摘要翻译：本发明提供了利用多晶硅间隔物的制造工艺来构建具有2bit / cell的闪速存储器的方法。在本发明中，凹入的多晶硅间隔物用于制造控制栅极下面的不连续的浮动栅极以构建具有2bit / cell的闪速存储器。本发明的特征在于，多晶硅间隔物的制造工艺被利用以完全以自动对准方式完成浮栅的制造工艺，而无需任何额外的掩模工艺。此外，该闪速存储器中的每个存储单元可以存储两个位，从而增加存储器容量。

27. 发明授权

US06713315B2 Mask read-only memory and fabrication thereof 有权
标题翻译：掩模只读存储器及其制造
公开(公告)号：US06713315B2
公开(公告)日：2004-03-30
申请号：US10134270
申请日：2002-04-25
申请人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
发明人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
IPC分类号： H01L2100
CPC分类号： H01L27/11266 , H01L27/105 , H01L27/11293
摘要： A method for fabricating a Mask ROM is described, in which an ONO composite layer and a plurality of gate structures are formed on a substrate. A plurality of bit-lines are formed in the substrate between the gate structures and a plurality of word-lines are formed over the substrate to electrically connect with the gate structures. A chemical vapor deposition anti-reflective coating (CVD-ARC) with coding windows therein and an inter-layer dielectric layer are formed over the substrate. A coding process is then performed by using UV light to form a plurality of charged coding regions in the charge trapping layer not covered by the CVD-ARC. A plurality of plugs are then formed in the coding windows.
摘要翻译：描述了一种用于制造掩模ROM的方法，其中在基板上形成ONO复合层和多个栅极结构。在栅极结构之间的衬底中形成多个位线，并且在衬底上形成多个字线以与栅极结构电连接。在其上形成了具有编码窗口的化学气相沉积抗反射涂层（CVD-ARC）和层间电介质层。然后通过使用UV光在未被CVD-ARC覆盖的电荷捕获层中形成多个带电编码区域来进行编码处理。然后在编码窗口中形成多个插头。

28. 发明授权

US06642113B1 Non-volatile memory capable of preventing antenna effect and fabrication thereof 有权
标题翻译：能够防止天线效应和制造的非易失性存储器
公开(公告)号：US06642113B1
公开(公告)日：2003-11-04
申请号：US10128742
申请日：2002-04-23
申请人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
发明人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
IPC分类号： H01L2100
CPC分类号： H01L29/66833 , H01L21/28282 , Y10S438/954
摘要： A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.
摘要翻译：描述能够防止天线效应及其制造的非易失性存储器。非易失性存储器包括在基板上具有高电阻部分和存储单元部分的字线以及位于字线和基板之间的电荷捕获层。高电阻部分与衬底中的接地掺杂区域电连接，并且存储单元部分与衬底上的金属互连电连接。

29. 发明授权

US06627500B1 Method of fabricating nitride read only memory 有权
标题翻译：制造氮化物只读存储器的方法
公开(公告)号：US06627500B1
公开(公告)日：2003-09-30
申请号：US10064796
申请日：2002-08-19
申请人： Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
发明人： Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/978
摘要： A method of fabricating a nitride read only memory. A trapping dielectric sandwiched structure, including an insulation layer, a charge trap layer and an insulation layer, is formed on a substrate. An opening with indented sidewalls is formed in the insulation layer. A thermal oxide layer is formed to fill the opening, such that the indented sidewalls are completely sealed. The charge trap layer is thus sealed by the insulation layers and the thermal oxide layer to avoid the direct contact between the control gate and the charge trap layer, so as to prevent the data loss.
摘要翻译：一种制造氮化物只读存储器的方法。在衬底上形成包括绝缘层，电荷陷阱层和绝缘层的俘获电介质夹层结构。在绝缘层中形成具有凹入侧壁的开口。形成热氧化物层以填充开口，使得凹入的侧壁被完全密封。因此，电荷陷阱层被绝缘层和热氧化物层密封，以避免控制栅极和电荷陷阱层之间的直接接触，从而防止数据丢失。

30. 发明授权

US06580630B1 Initialization method of P-type silicon nitride read only memory 有权
标题翻译： P型氮化硅只读存储器的初始化方法
公开(公告)号：US06580630B1
公开(公告)日：2003-06-17
申请号：US10165715
申请日：2002-06-07
申请人： Chien-Hung Liu , Shou-Wei Huang , Shyi-Shuh Pan
发明人： Chien-Hung Liu , Shou-Wei Huang , Shyi-Shuh Pan
IPC分类号： G11C1300
CPC分类号： H01L29/66833 , G11C16/18 , H01L21/28282 , H01L29/792
摘要： The presents invention provides an initialization method of a P-type silicon nitride read only memory. A P-type silicon nitride read only memory is provided. An ultra-violet light is uniformly radiated onto the P-type silicon nitride read only memory. Electron traps are thus evenly distributed in a silicon nitride layer of the P-type silicon nitride read only memory. The P-type silicon nitride read only memory is thus uniformly programmed to a low threshold voltage (Low|Vt|) to achieve the device initialization effect.
摘要翻译：本发明提供了一种P型氮化硅只读存储器的初始化方法。提供了P型氮化硅只读存储器。紫外光均匀地辐射到P型氮化硅只读存储器上。因此，电子俘获器均匀分布在P型氮化硅只读存储器的氮化硅层中。因此，P型氮化硅只读存储器被均匀地编程到低阈值电压（Low | Vt |）以实现器件初始化效果。

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