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21. 发明授权

US5586278A Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor 失效
标题翻译：在无序微处理器中的分支错误预测之后状态恢复的方法和装置
公开(公告)号：US5586278A
公开(公告)日：1996-12-17
申请号：US639244
申请日：1996-04-22
申请人： David B. Papworth , Glenn J. Hinton
发明人： David B. Papworth , Glenn J. Hinton
IPC分类号： G06F9/38
CPC分类号： G06F9/3863
摘要： A method of state recovery following a branch misprediction or an undetected branch instruction. If, during execution of a branch instruction in an out-of-order unit, it is determined that the branch has been mispredicted, or if a taken branch has not been detected, then a JEClear signal is asserted to flush the instruction fetch unit and decoder section, and to change the instruction pointer to the actual target address. Within the out-of-order section, the instructions preceding the branch instruction are allowed to continue execution and proceed to in-order retirement. Simultaneously, instructions fetched at the actual target address are decoded, but not allowed to issue therefrom until the branch instruction has been retired from the out-of-order section, after which all instructions within the out-of-order section are flushed, and then decoded instructions are allowed to issue from the decoder. The state recovery method advantageously provides efficient utilization of processor time.
摘要翻译：分支错误预测或未检测到的分支指令之后的状态恢复方法。如果在执行无序单元中的分支指令时，确定分支已经被错误预测，或者如果未被检测到被采取的分支，则断言JEClear信号以刷新指令获取单元，并且解码器部分，并将指令指针更改为实际目标地址。在无序部分中，分支指令之前的指令被允许继续执行，并进行到订单退休。同时，在实际目标地址处获取的指令被解码，但是在分支指令已经从无序部分退出之前不允许发出指令，之后清除无序部分内的所有指令，以及则解码指令被允许从解码器发出。状态恢复方法有利地提供了处理器时间的有效利用。

22. 发明授权

US5584037A Entry allocation in a circular buffer 失效
标题翻译：循环缓冲区中的条目分配
公开(公告)号：US5584037A
公开(公告)日：1996-12-10
申请号：US571377
申请日：1995-12-13
申请人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
发明人： David B. Papworth , Andrew F. Glew , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , Steven J. Griffith , Shantanu R. Gupta , Narayan Hegde
IPC分类号： G06F5/10 , G06F5/14 , G06F9/38 , G06F12/00
CPC分类号： G06F5/14 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： An allocator assigns entries for a circular buffer. The allocator receives requests for storing data in entries of the circular buffer, and generates a head pointer to identify a starting entry in the circular buffer for which circular buffer entries are not allocated. In addition to pointing to an entry in the circular buffer, the head pointer includes a wrap bit. The allocator toggles the wrap bit each time the allocator traverses the linear queue of the circular buffer. A tail pointer is generated, including the wrap bit, to identify an ending entry in the circular buffer for which circular buffer entries are allocated. In response to the request for entries, the allocator sequentially assigns entries for the requests located between the head pointer and the tail pointer. The allocator has application for use in a microprocessor performing out-of-order dispatch and speculative execution. The allocator is coupled to a reorder buffer, configured as a circular buffer, to permit allocation of entries. The allocator utilizes an all or nothing allocation policy, such that either all or no incoming instructions are allocated during an allocation period.
摘要翻译：分配器为循环缓冲区分配条目。分配器接收在循环缓冲器的条目中存储数据的请求，并且生成头指针以标识不分配循环缓冲器条目的循环缓冲器中的起始条目。除了指向循环缓冲区中的条目之外，头指针还包括一个换行位。每次分配器遍历循环缓冲区的线性队列时，分配器将切换换行。生成尾指针，包括换行位，以标识分配循环缓冲区条目的循环缓冲区中的结尾条目。响应于条目请求，分配器顺序分配位于头部指针和尾部指针之间的请求的条目。分配器具有用于执行无序调度和推测执行的微处理器的应用。分配器被耦合到配置为循环缓冲器的重排序缓冲器，以允许分配条目。分配器利用全部或全部分配策略，使得在分配周期期间分配全部或者没有传入指令。

23. 发明授权

US5574871A Method and apparatus for implementing a set-associative branch target buffer 失效
公开(公告)号：US5574871A
公开(公告)日：1996-11-12
申请号：US177155
申请日：1994-01-04
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

24. 发明授权

US5564111A Method and apparatus for implementing a non-blocking translation lookaside buffer 失效
标题翻译：用于实现非阻塞转换后备缓冲器的方法和装置
公开(公告)号：US5564111A
公开(公告)日：1996-10-08
申请号：US315833
申请日：1994-09-30
申请人： Andrew F. Glew , Haitham Akkary , Robert P. Colwell , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman
发明人： Andrew F. Glew , Haitham Akkary , Robert P. Colwell , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman
IPC分类号： G06F9/38 , G06F11/00 , G06F12/10 , G06F11/34
CPC分类号： G06F9/3865 , G06F11/0751 , G06F12/1027 , G06F9/3842 , G06F2212/684
摘要： A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions. Upon retirement of each instruction, the reordering buffer determines whether a fault had been detected for that instruction and, if so, the microprocessor is flushed. Then, a branch is taken into microcode. The microcode accesses the linear address and other information stored within the fault register of the translation lookaside buffer and handles the fault. The system is flushed and the microcode is executed only for faulting instructions which actually retire. As such, faults detected while processing speculative instructions based upon mispredicted branches do not prevent further address translations and do not cause the system to be flushed. Method and apparatus implementations are described herein.
摘要翻译：描述了用于能够处理推测和乱序指令的微处理器中的非阻塞转换后备缓冲器。在检测到故障时，无论是在翻译后备缓冲器命中还是响应于翻译后备缓冲器未命中执行的页表行走期间，与故障指令相关联的信息都存储在翻译后备缓冲器内的故障寄存器内。所存储的信息包括指令的线性地址和识别指令年龄的信息。除了将信息存储在故障寄存器之外，信息的一部分被发送到微处理器的重排序缓冲器以便存储在故障指令中。在故障指令退出之前，翻译后备缓冲区继续处理进一步的指令。在每个指令退出后，重新排序缓冲器确定是否检测到该指令发生故障，如果是，则清除微处理器。然后，一个分支被带入微码。微代码访问存储在翻译后备缓冲区的故障寄存器内的线性地址和其他信息，并处理故障。系统被刷新，微代码仅对实际退出的故障指令执行。因此，基于错误预测的分支处理推测性指令时检测到的故障不会妨碍进一步的地址转换，并且不会导致系统被刷新。本文描述了方法和装置实现。

25. 发明授权

US5471633A Idiom recognizer within a register alias table 失效
标题翻译：注册表中的成语识别器
公开(公告)号：US5471633A
公开(公告)日：1995-11-28
申请号：US205842
申请日：1994-03-01
申请人： Robert P. Colwell , Andrew F. Glew , David B. Papworth , Glenn J. Hinton , David W. Clift
发明人： Robert P. Colwell , Andrew F. Glew , David B. Papworth , Glenn J. Hinton , David W. Clift
IPC分类号： G06F9/30 , G06F9/38 , G06F7/00
CPC分类号： G06F9/3824 , G06F9/30112 , G06F9/3826 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A register alias table unit (RAT) with an idiom recognition mechanism for overriding partial width conditions stalls is described. A partial width stall condition occurs during the RAT renaming process when a logical source register being renamed is larger than the corresponding physical source register pointed to by a renaming table. An idiom recognizer detects uops that zero their logical destination register and sets and clears zero bits in an iRAT array accordingly. The zero bits indicate which portions of an entry's physical source register are known to be zeros. A partial width stall override mechanism overrides a partial width stall condition when the zero bits for the physical source register causing the partial width stall indicate that the "missing" portion of the physical source register contains zeros. The performance of a microprocessor implementing such a RAT renaming mechanism with an idiom recognizer is improved because common partial width stalls are avoided.
摘要翻译：描述了具有用于覆盖部分宽度条件失速的习惯识别机制的寄存器别名表单元（RAT）。当重新命名的逻辑源寄存器大于重命名表指向的相应物理源寄存器时，在RAT重命名过程期间发生部分宽度失速状况。成语识别器检测uops，使其逻辑目标寄存器为零，并相应地设置和清除iRAT阵列中的零位。零位指示条目的物理源寄存器的哪些部分已知为零。当导致部分宽度失速的物理源寄存器的零位指示物理源寄存器的“丢失”部分包含零时，部分宽度失速覆盖机制将覆盖部分宽度失速条件。通过习惯识别器实现这种RAT重命名机构的微处理器的性能得到改善，因为避免了普通的部分宽度档位。

26. 发明授权

US5420991A Apparatus and method for maintaining processing consistency in a computer system having multiple processors 失效
标题翻译：用于在具有多个处理器的计算机系统中维持处理一致性的装置和方法
公开(公告)号：US5420991A
公开(公告)日：1995-05-30
申请号：US177239
申请日：1994-01-04
申请人： Kris G. Konigsfeld , Jeffrey M. Abramson , Haitham Akkary , Glenn J. Hinton , Andrew F. Glew
发明人： Kris G. Konigsfeld , Jeffrey M. Abramson , Haitham Akkary , Glenn J. Hinton , Andrew F. Glew
IPC分类号： G06F9/312 , G06F9/38 , G06F12/08 , G06F9/46
CPC分类号： G06F9/30043 , G06F12/0831 , G06F9/3834
摘要： An apparatus for maintaining processor ordering in a multi-processor computer system wherein loads are performed speculatively. Speculative loads of each processor are temporarily stored in their respective processors' load buffer. When one of the processors performs a store, a snoop operation is performed on the other processors' load buffers. If the snoop results in a hit, a determination is made as to whether that load buffer contains any prior conflicting speculative loads which have been completed. If the load buffer does contain a prior conflicting load, a processor ordering violation signal is generated. In response to this signal, the violating load and all subsequent operations are canceled and re-executed at a later time.
摘要翻译：一种用于在多处理器计算机系统中维持处理器排序的装置，其中负载被推测地执行。每个处理器的推测负载临时存储在它们各自的处理器的负载缓冲器中。当其中一个处理器执行存储时，对其他处理器的负载缓冲区执行窥探操作。如果窥探导致命中，则确定该加载缓冲器是否包含已经完成的任何先前冲突的推测负载。如果加载缓冲区确实包含先前存在冲突的负载，则会生成处理器排序违规信号。响应于该信号，违反负载和所有后续操作将在以后被取消并重新执行。

27. 发明授权

US08407489B2 Method and apparatus for quick resumption 有权
公开(公告)号：US08407489B2
公开(公告)日：2013-03-26
申请号：US12384673
申请日：2009-04-07
申请人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
发明人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
IPC分类号： G06F9/24 , G06F15/177
CPC分类号： G06F1/3234 , G06F9/4418
摘要： When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.

28. 发明申请

US20120166891A1 TWO-LEVEL SYSTEM MAIN MEMORY 有权
标题翻译：两级系统主要内存
公开(公告)号：US20120166891A1
公开(公告)日：2012-06-28
申请号：US12976545
申请日：2010-12-22
申请人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
发明人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
IPC分类号： G06F11/16 , G06F12/00
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0685 , G06F11/0766 , G06F12/0246 , G06F12/0638 , G06F12/0868 , G06F12/0893 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C14/009
摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
摘要翻译：本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。远存储器可以经由低带宽，高延迟装置耦合到CPU。

29. 发明授权

US08171219B2 Method and system to perform caching based on file-level heuristics 有权
标题翻译：基于文件级启发式方法和系统执行缓存
公开(公告)号：US08171219B2
公开(公告)日：2012-05-01
申请号：US12415595
申请日：2009-03-31
申请人： Sanjeev N. Trika , Amber D. Huffman , James A. Boyd , Frank T. Hady , Glenn J. Hinton , Dale J. Juenemann , Oscar P. Pinto , Scott R. Tetrick , Thomas J. Barnes , Scott E. Burridge
发明人： Sanjeev N. Trika , Amber D. Huffman , James A. Boyd , Frank T. Hady , Glenn J. Hinton , Dale J. Juenemann , Oscar P. Pinto , Scott R. Tetrick , Thomas J. Barnes , Scott E. Burridge
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0866 , G06F12/0888 , G06F12/121 , G06F2212/222 , G06F2212/6028
摘要： A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.
摘要翻译：至少基于一个或多个文件级启发式方法和系统执行缓存。缓存设备中的存储介质的缓存由高速缓存策略引擎执行。高速缓存策略引擎接收存储介质的数据的输入/输出访问的文件级信息，并基于接收到的文件级信息来高速缓存或者将高速缓存设备中的存储介质的数据移出。通过利用关于与存储介质的磁盘扇区或逻辑块地址相关联的文件和文件操作的信息，高速缓存策略引擎可以更好地决定要缓存到缓存设备或从高速缓存设备移出的存储介质的数据选择在本发明的一个实施例中。可以实现更高的缓存命中率，并提高利用缓存策略引擎的系统的性能。

30. 发明申请

US20090271641A1 Method and apparatus for quick resumption 有权
公开(公告)号：US20090271641A1
公开(公告)日：2009-10-29
申请号：US12384673
申请日：2009-04-07
申请人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
发明人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
IPC分类号： G06F1/00
CPC分类号： G06F1/3234 , G06F9/4418
摘要： When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.

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