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21. 发明申请

US20140195817A1 THREE INPUT OPERAND VECTOR ADD INSTRUCTION THAT DOES NOT RAISE ARITHMETIC FLAGS FOR CRYPTOGRAPHIC APPLICATIONS 审中-公开
标题翻译：三个输入操作向量添加指令，不提供用于CRYPTOAPHAPH应用的算术标记
公开(公告)号：US20140195817A1
公开(公告)日：2014-07-10
申请号：US13996527
申请日：2011-12-23
申请人： Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Gilbert M. Wolrich , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon
发明人： Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Gilbert M. Wolrich , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon
IPC分类号： G06F21/60 , G06F9/30
CPC分类号： G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30181
摘要： A method is described that includes performing the following within an instruction execution pipeline implemented on a semiconductor chip: summing three input vector operands through execution of a single instruction; and, not raising any arithmetic flags even though a result of the summing creates more bits than circuitry designed to transport the summation is able to transport.
摘要翻译：描述了一种方法，其包括在半导体芯片上实现的指令执行流水线内执行以下操作：通过执行单个指令对三个输入向量操作数相加; 并且，即使求和的结果产生比设计用于传送求和的电路更多的位能够传输，也不会提高任何算术标记。

22. 发明申请

US20140053000A1 INSTRUCTIONS TO PERFORM JH CRYPTOGRAPHIC HASHING 有权
标题翻译：执行JH CRYPTOGRAPHIC HASHING的指示
公开(公告)号：US20140053000A1
公开(公告)日：2014-02-20
申请号：US13992225
申请日：2011-12-22
申请人： Kirk S. Yap , Gilbert M. Wolrich , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F21/64
CPC分类号： G06F21/64 , H04L9/0643 , H04L2209/12
摘要： A method is described. The method includes executing one or more JH_SBOX_L instruction to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_Permute instruction to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed
摘要翻译：描述了一种方法。该方法包括在JH状态下执行一个或多个JH_SBOX_L指令来执行S-Box映射和线性（L）变换，并且一旦S-Box映射和 L变换

23. 发明申请

US20140019693A1 PARALLEL PROCESSING OF A SINGLE DATA BUFFER 审中-公开
标题翻译：单个数据缓冲器的并行处理
公开(公告)号：US20140019693A1
公开(公告)日：2014-01-16
申请号：US13631761
申请日：2012-09-28
申请人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： G06F12/00
CPC分类号： G06F5/06 , G06F21/64 , H04L9/0643 , H04L9/3236 , H04L2209/12 , H04L2209/20
摘要： Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm.
摘要翻译：用于在单个可变长度数据缓冲器上执行串行数据处理算法的技术包括缓冲器的流片段到数据寄存器中，并行地对每个片段执行算法，并且在每个片段上合并执行算法的结果形成串行数据处理算法的输出。

24. 发明申请

US20150098563A1 Generating Multiple Secure Hashes from a Single Data Buffer 有权
标题翻译：从单个数据缓冲区生成多个安全哈希
公开(公告)号：US20150098563A1
公开(公告)日：2015-04-09
申请号：US14050326
申请日：2013-10-09
申请人： Sean M. Gulley , Vinodh Gopal , Wajdi K. Feghali , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Vinodh Gopal , Wajdi K. Feghali , James D. Guilford , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： H04L9/06
CPC分类号： H04L9/0643 , G06F9/30007 , G06F21/72 , H04L9/3242 , H04L2209/12 , H04L2209/125 , H04L2209/20
摘要： One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.
摘要翻译：一个实施例提供了一种装置。该装置包括单个指令多数据（SIMD）散列模块，其被配置为将长度为L的消息的至少第一部分分配给数量（S）个段，该消息包括多个数据元素序列，每个序列包括 S个数据元素，分配给相应段的每个序列中的相应数据元素，每个段包括N个数据元素块，并且并行地对S个段进行散列，导致S段摘要，基于S个散列摘要至少部分地在初始值上存储S哈希摘要; 填充模块，被配置为填补余数，剩余部分对应于消息的第二部分，与消息的长度L相关的第二部分，段的数量和块大小; 以及非SIMD散列模块，被配置为对填充的余数进行散列，产生附加的散列摘要并存储附加散列摘要。

25. 发明授权

US09419792B2 Instruction for accelerating SNOW 3G wireless security algorithm 有权
标题翻译：加速SNOW 3G无线安全算法的指令
公开(公告)号：US09419792B2
公开(公告)日：2016-08-16
申请号：US13730216
申请日：2012-12-28
申请人： Gilbert M. Wolrich , Vinodh Gopal , Erdinc Ozturk , Kirk S. Yap , Wajdi K. Feghali
发明人： Gilbert M. Wolrich , Vinodh Gopal , Erdinc Ozturk , Kirk S. Yap , Wajdi K. Feghali
IPC分类号： G06F15/00 , G06F7/00 , H04L9/06 , G09C1/00 , H04L29/06 , H04W12/02
CPC分类号： H04W12/02 , G06F9/30007 , G06F9/30036 , G06F9/30134 , G06F9/3887 , G09C1/00 , H04L9/065 , H04L9/0668 , H04L63/045 , H04L63/0457 , H04W12/04
摘要： Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry also receives a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM. The execution circuitry executes the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.
摘要翻译：用于执行SNOW 3G无线安全操作的矢量指令由处理器的执行电路接收和执行。执行电路接收指定存储有限状态机（FSM）的当前状态的第一向量寄存器的第一指令的第一操作数。执行电路还接收指定第二向量寄存器的第一指令的第二操作数，该第二指令寄存器存储用于更新FSM所需的线性反馈移位寄存器（LFSR）的数据元素。执行电路执行第一指令以产生FSM的更新状态和FSM在第一指令的目的地操作数中的输出。

26. 发明申请

US20140189289A1 INSTRUCTION FOR ACCELERATING SNOW 3G WIRELESS SECURITY ALGORITHM 有权
标题翻译：加速雪的指令3G无线安全算法
公开(公告)号：US20140189289A1
公开(公告)日：2014-07-03
申请号：US13730216
申请日：2012-12-28
申请人： Gilbert M. Wolrich , Vinodh Gopal , Erdinc Ozturk , Kirk S. Yap , Wajdi K. Feghali
发明人： Gilbert M. Wolrich , Vinodh Gopal , Erdinc Ozturk , Kirk S. Yap , Wajdi K. Feghali
IPC分类号： G06F15/80
CPC分类号： H04W12/02 , G06F9/30007 , G06F9/30036 , G06F9/30134 , G06F9/3887 , G09C1/00 , H04L9/065 , H04L9/0668 , H04L63/045 , H04L63/0457 , H04W12/04
摘要： Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry also receives a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM. The execution circuitry executes the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.
摘要翻译：用于执行SNOW 3G无线安全操作的矢量指令由处理器的执行电路接收和执行。执行电路接收指定存储有限状态机（FSM）的当前状态的第一向量寄存器的第一指令的第一操作数。执行电路还接收指定第二向量寄存器的第一指令的第二操作数，该第二指令寄存器存储用于更新FSM所需的线性反馈移位寄存器（LFSR）的数据元素。执行电路执行第一指令以产生FSM的更新状态和FSM在第一指令的目的地操作数中的输出。

27. 发明申请

US20160092688A1 INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM3 CRYPTOGRAPHIC HASHING FUNCTIONALITY 有权
标题翻译：说明和逻辑提供SIMD SM3 CRYPTOGRAPHIC HASHING功能
公开(公告)号：US20160092688A1
公开(公告)日：2016-03-31
申请号：US14498931
申请日：2014-09-26
申请人： Gilbert M. Wolrich , Vinodh Gopal , Sean M. Gulley , Kirk S. Yap , Wajdi K. Feghali
发明人： Gilbert M. Wolrich , Vinodh Gopal , Sean M. Gulley , Kirk S. Yap , Wajdi K. Feghali
IPC分类号： G06F21/60 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30007 , G06F9/30036 , G06F21/72
摘要： Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.
摘要翻译：说明和逻辑提供SIMD SM3加密散列功能。一些实施例包括处理器，包括：解码器，用于解码SIMD SM3消息扩展的指令，指定第一和第二源数据操作数集合以及扩展范围。响应于指令的处理器执行单元从由指定扩展范围确定的第一和第二源数据操作数集执行多个SM3消息扩展，并将结果存储到SIMD目的地寄存器中。一些实施例还从中间散列值输入，源数据集和圆常数集合执行散列算法的SIMD SM3散列圆切片部分的指令。处理器执行单元在源数据集上执行一组SM3散列循环迭代，应用中间散列值输入和循环常数集合，并将新的散列值结果存储在SIMD目的寄存器中。

28. 发明申请

US20140019694A1 PARALLELL PROCESSING OF A SINGLE DATA BUFFER 审中-公开
标题翻译：单数据缓冲器的并行处理
公开(公告)号：US20140019694A1
公开(公告)日：2014-01-16
申请号：US13631763
申请日：2012-09-28
申请人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert Wolrich , Kirk S. Yap
IPC分类号： G06F12/00
CPC分类号： G06F5/06 , G06F21/64 , H04L9/0643 , H04L9/3236 , H04L2209/12 , H04L2209/20
摘要： Technologies for executing a serial data processing algorithm on a single variable-length data buffer includes padding data segments of the buffer, streaming the data segments into a data register and executing the serial data processing algorithm on each of the segments in parallel.
摘要翻译：用于在单个可变长度数据缓冲器上执行串行数据处理算法的技术包括缓冲器的填充数据段，将数据段流传输到数据寄存器中，并且并行地对每个段执行串行数据处理算法。

29. 发明申请

US20140093069A1 INSTRUCTION SET FOR MESSAGE SCHEDULING OF SHA256 ALGORITHM 有权
标题翻译： SHA256算法的消息调度指令集
公开(公告)号：US20140093069A1
公开(公告)日：2014-04-03
申请号：US13631165
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Sean M. Gulley
发明人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Sean M. Gulley
IPC分类号： H04L9/28
CPC分类号： G09C1/00 , G06F9/30007 , H04L9/0643 , H04L2209/125
摘要： A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.
摘要翻译：处理器包括第一执行单元，用于接收和执行第一指令以处理安全散列算法256（SHA256）消息调度操作的第一部分，所述第一指令具有与第一存储位置相关联的第一操作数，以存储第一组消息输入和与第二存储位置相关联的第二操作数，以存储第二组消息输入。所述处理器还包括第二执行单元，用于接收和执行用于处理所述SHA256消息调度操作的第二部分的第二指令，所述第二指令具有与第三存储位置相关联的第三操作数，以存储所述第一部分的中间结果;以及第三组消息输入和与第四存储位置相关联的第四操作数，以存储第四组消息输入。

30. 发明授权

US08874933B2 Instruction set for SHA1 round processing on 128-bit data paths 有权
标题翻译： 128位数据路径SHA1循环处理指令集
公开(公告)号：US08874933B2
公开(公告)日：2014-10-28
申请号：US13631150
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
IPC分类号： G06F21/22
CPC分类号： G06F21/72 , G06F9/30007 , G06F9/30036 , H04L9/0643
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA states, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理SHA1散列算法的第一指令，所述第一指令具有第一操作数，第二操作数和第三操作数，所述第一操作数指定存储四个 SHA指出，第二操作数指定存储与第五SHA1状态相结合的多个SHA1消息输入的第二存储位置。所述处理器还包括执行单元，其响应于所述第一指令而耦合到所述指令解码器，以使用所述第一和第二操作数获得的所述SHA1状态和从所述第一和第二操作数获得的所述消息输入执行至少四轮所述SHA1循环操作，逻辑功能在第三个操作数中指定。

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