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21. 发明申请

US20070177427A1 Nonvolatile memory device and method thereof 审中-公开
标题翻译：非易失性存储器件及其方法
公开(公告)号：US20070177427A1
公开(公告)日：2007-08-02
申请号：US11698071
申请日：2007-01-26
申请人： Geon-Woo Park , Geum-Jong Bae , In-Wook Cho , Byoung-Jin Lee , Myung-Yoon Um , Sang-Chul Lee
发明人： Geon-Woo Park , Geum-Jong Bae , In-Wook Cho , Byoung-Jin Lee , Myung-Yoon Um , Sang-Chul Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0425 , G11C16/04 , G11C16/0466 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C29/50 , G11C29/50004 , G11C2029/5002
摘要： A nonvolatile memory device and method thereof are provided. The example method may include applying a first bias voltage to a gate electrode, applying a second bias voltage to a substrate to obtain a first voltage potential difference between the gate electrode and the substrate and applying a third bias voltage to a first impurity region to obtain a second voltage potential difference between the substrate and the first impurity region, the first and third bias voltages being positive and the second bias voltage being negative. The example nonvolatile memory device may include a gate electrode receiving a first bias voltage, a substrate receiving a second bias voltage, the first and second bias voltages forming a first voltage potential difference between the gate electrode and the substrate and a first impurity region receiving a third bias voltage, the second and third bias voltages forming a second voltage potential difference between the first impurity region and the substrate, the first and third bias voltages being positive and the second bias voltage being negative.
摘要翻译：提供了一种非易失性存储器件及其方法。示例性方法可以包括向栅电极施加第一偏置电压，向衬底施加第二偏置电压以获得栅电极和衬底之间的第一电压电位差，并向第一杂质区域施加第三偏置电压以获得所述基板和所述第一杂质区域之间的第二电压电位差，所述第一和第三偏置电压为正，所述第二偏置电压为负。示例性非易失性存储器件可以包括接收第一偏置电压的栅电极，接收第二偏置电压的衬底，在栅电极和衬底之间形成第一电压电位差的第一和第二偏置电压以及接收第所述第二偏置电压和所述第三偏置电压在所述第一杂质区域和所述衬底之间形成第二电压电位差，所述第一和第三偏置电压为正，所述第二偏置电压为负。

22. 发明申请

US20050153514A1 Method of manufacturing dielectric layer in non-volatile memory cell 有权
标题翻译：在非易失性存储单元中制造介质层的方法
公开(公告)号：US20050153514A1
公开(公告)日：2005-07-14
申请号：US11033156
申请日：2005-01-12
申请人： Jai-Dong Lee , Ki-Chul Kim , In-Wook Cho
发明人： Jai-Dong Lee , Ki-Chul Kim , In-Wook Cho
IPC分类号： H01L27/115 , H01L21/314 , H01L21/336 , H01L21/8246 , H01L21/3205 , H01L21/31
CPC分类号： H01L21/022 , H01L21/02329 , H01L21/0234 , H01L21/3144 , H01L27/11568 , H01L29/66833
摘要： A method for manufacturing a dielectric layer structure for a non-volatile memory cell is provided. A method includes forming a first dielectric layer for tunneling on a semiconductor substrate, a second dielectric layer on the first dielectric layer to store charges, nitrogenizing surface of the second dielectric layer, and forming a third dielectric layer the nitridedsecond dielectric layer.
摘要翻译：提供一种用于制造用于非易失性存储单元的电介质层结构的方法。一种方法包括形成用于在半导体衬底上隧穿的第一电介质层，在第一电介质层上形成第二电介质层以存储电荷，使第二电介质层的氮化表面，以及形成第三介电层氮化二次介电层。

23. 发明授权

US07361560B2 Method of manufacturing a dielectric layer in a memory device that includes nitriding step 有权
标题翻译：在包括氮化步骤的存储器件中制造介电层的方法
公开(公告)号：US07361560B2
公开(公告)日：2008-04-22
申请号：US11033156
申请日：2005-01-12
申请人： Jai-Dong Lee , Ki-Chul Kim , In-Wook Cho
发明人： Jai-Dong Lee , Ki-Chul Kim , In-Wook Cho
IPC分类号： H01L21/336
CPC分类号： H01L21/022 , H01L21/02329 , H01L21/0234 , H01L21/3144 , H01L27/11568 , H01L29/66833
摘要： A method for manufacturing a dielectric layer structure for a non-volatile memory cell is provided. A method includes forming a first dielectric layer for tunneling on a semiconductor substrate, a second dielectric layer on the first dielectric layer to store charges, nitrogenizing surface of the second dielectric layer, and forming a third dielectric layer the nitridedsecond dielectric layer.
摘要翻译：提供一种用于制造用于非易失性存储单元的电介质层结构的方法。一种方法包括形成用于在半导体衬底上隧穿的第一电介质层，在第一电介质层上形成第二电介质层以存储电荷，使第二电介质层的氮化表面，以及形成第三介电层氮化二次介电层。

24. 发明授权

US07932154B2 Method of fabricating non-volatile flash memory device having at least two different channel concentrations 失效
标题翻译：制造具有至少两个不同通道浓度的非易失性闪速存储器件的方法
公开(公告)号：US07932154B2
公开(公告)日：2011-04-26
申请号：US12007097
申请日：2008-01-07
申请人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
发明人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
IPC分类号： H01L21/334
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.
摘要翻译：在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案，电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及覆盖屏蔽层图案的栅电极和栅极绝缘层。

25. 发明申请

US20080108197A1 Method of fabricating non-volatile flash memory device having at least two different channel concentrations 失效
标题翻译：制造具有至少两个不同通道浓度的非易失性闪速存储器件的方法
公开(公告)号：US20080108197A1
公开(公告)日：2008-05-08
申请号：US12007097
申请日：2008-01-07
申请人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
发明人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
IPC分类号： H01L21/334
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.
摘要翻译：在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案，电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及覆盖屏蔽层图案的栅电极和栅极绝缘层。

26. 发明授权

US07320920B2 Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same 失效
标题翻译：具有至少两种不同通道浓度的非挥发性闪存器件及其制造方法
公开(公告)号：US07320920B2
公开(公告)日：2008-01-22
申请号：US11097281
申请日：2005-04-04
申请人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
发明人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
IPC分类号： H01L21/334
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.
摘要翻译：在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案，电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及覆盖屏蔽层图案的栅电极和栅极绝缘层。

27. 发明申请

US20060011965A1 Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same 失效
标题翻译：具有至少两种不同通道浓度的非挥发性闪存器件及其制造方法
公开(公告)号：US20060011965A1
公开(公告)日：2006-01-19
申请号：US11097281
申请日：2005-04-04
申请人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
发明人： Sang-Su Kim , Sung-Taeg Kang , In-Wook Cho , Jeong-Hwan Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/792
摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.
摘要翻译：在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案，电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及覆盖屏蔽层图案的栅电极和栅极绝缘层。

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