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21. 发明授权

US06654870B1 Methods and apparatus for establishing port priority functions in a VLIW processor 有权
标题翻译：在VLIW处理器中建立端口优先功能的方法和装置
公开(公告)号：US06654870B1
公开(公告)日：2003-11-25
申请号：US09598084
申请日：2000-06-21
申请人： Edwin Frank Barry , Edward A. Wolff , Patrick Rene Marchand , David Carl Strube
发明人： Edwin Frank Barry , Edward A. Wolff , Patrick Rene Marchand , David Carl Strube
IPC分类号： G06F938
CPC分类号： G06F9/30141 , G06F9/30003 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/3016 , G06F9/3838 , G06F9/3853 , G06F9/3885
摘要： Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For. example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1. Other unique capabilities result from the present approach to assigning port priorities that improve the performance of the ManArray indirect VLIW processor.
摘要翻译：端口优先级定义在32位字，16位半字和8位字节的基础上，用于将写使能信号控制到计算寄存器文件（CRF）。使用歧管阵列（ManArray）可重配置寄存器文件，可以将双字64位和单字32位数据类型指令与其他双字，单字，半字或字节数据混合类型的指令在相同的很长的指令字（VLIW）内。通过在VLIW执行期间解决冲突的字节，半字或字的写入优先级冲突，可以使部分操作完成，从而提供有用的功能。对于。例如，到32位寄存器R0的半字H0部分的加载半字可以优先完成其操作，而寄存器对R0和R1的64位移位将完成其在非冲突的操作 64位寄存器R0和R1的半字部分。目前的分配端口优先级方法的其他独特功能来自于提高ManArray间接VLIW处理器的性能。

22. 发明授权

US07024540B2 Methods and apparatus for establishing port priority functions in a VLIW processor 失效
标题翻译：在VLIW处理器中建立端口优先功能的方法和装置
公开(公告)号：US07024540B2
公开(公告)日：2006-04-04
申请号：US10695071
申请日：2003-10-28
申请人： Edwin Frank Barry , Edward A. Wolff , Patrick Rene Marchand , David Carl Strube
发明人： Edwin Frank Barry , Edward A. Wolff , Patrick Rene Marchand , David Carl Strube
IPC分类号： G06F12/00
CPC分类号： G06F9/30141 , G06F9/30003 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/3016 , G06F9/3838 , G06F9/3853 , G06F9/3885
摘要： Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1. Other unique capabilities result from the present approach to assigning port priorities that improve the performance of the ManArray indirect VLIW processor.
摘要翻译：端口优先级定义在32位字，16位半字和8位字节的基础上，用于将写使能信号控制到计算寄存器文件（CRF）。使用歧管阵列（ManArray）可重配置寄存器文件，可以将双字64位和单字32位数据类型指令与其他双字，单字，半字或字节数据混合类型的指令在相同的很长的指令字（VLIW）内。通过在VLIW执行期间解决冲突的字节，半字或字的写入优先级冲突，可以使部分操作完成，从而提供有用的功能。例如，对于32位寄存器R 0的半字H 0部分的加载半字可以优先完成其操作，而寄存器对R 0和R 1的64位移位将完成其操作在64位寄存器R 0和R 1的非冲突半字部分上。其他独特功能来自本方法分配端口优先级，以提高ManArray间接VLIW处理器的性能。

23. 发明授权

US08156261B2 Methods and apparatus for providing data transfer control 有权
标题翻译：提供数据传输控制的方法和装置
公开(公告)号：US08156261B2
公开(公告)日：2012-04-10
申请号：US13037619
申请日：2011-03-01
申请人： Edwin Franklin Barry , Edward A. Wolff
发明人： Edwin Franklin Barry , Edward A. Wolff
IPC分类号： G06F13/28 , G06F3/00 , G06F13/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.
摘要翻译：描述了用于在数据处理系统内改进数据传输控制的各种有利机制。描述了一种DMA控制器，其被实现为支持多个传输控制器的多处理传输引擎，其可以独立地或协作地执行数据传输，每个传输控制器充当自治处理器，将DMA指令提取并分派给多个执行单元。特别地，提供了用于启动和控制数据传输序列的机制，以及自动获取被顺序解码但并行执行的DMA指令的过程。每个传输控制器内的双传送执行单元与独立的传输计数器一起被用于允许源和目标地址生成的解耦，并允许一个传送执行单元中的多个传输指令与另一个传输中的单个传输指令并行操作单元。通过使用特殊信号量操作，信号和消息同步，可以使用SIGNAL和WAIT类型指令明确地调用，或者通过使用特殊的“事件动作”寄存器来隐式地调用源和目标之间的数据流改进。还描述了可以协作执行“DMA到DMA”传输的传输控制器。传输控制器可以使用消息级同步来相互同步。

24. 发明授权

US07908409B2 Methods and apparatus for providing data transfer control 有权
标题翻译：提供数据传输控制的方法和装置
公开(公告)号：US07908409B2
公开(公告)日：2011-03-15
申请号：US12536568
申请日：2009-08-06
申请人： Edwin Franklin Barry , Edward A. Wolff
发明人： Edwin Franklin Barry , Edward A. Wolff
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.
摘要翻译：描述了用于在数据处理系统内改进数据传输控制的各种有利机制。描述了一种DMA控制器，其被实现为支持多个传输控制器的多处理传输引擎，其可以独立地或协作地执行数据传输，每个传输控制器充当自治处理器，将DMA指令提取并分派给多个执行单元。特别地，提供了用于启动和控制数据传输序列的机制，以及自动获取被顺序解码但并行执行的DMA指令的过程。每个传输控制器内的双传送执行单元与独立的传输计数器一起被用于允许源和目标地址生成的解耦，并允许一个传送执行单元中的多个传输指令与另一个传输中的单个传输指令并行操作单元。通过使用特殊信号量操作，信号和消息同步，可以使用SIGNAL和WAIT类型指令明确地调用，或者通过使用特殊的“事件动作”寄存器来隐式地调用源和目标之间的数据流改进。还描述了可以协作执行“DMA到DMA”传输的传输控制器。传输控制器可以使用消息级同步来相互同步。

25. 发明授权

US07627698B2 Methods and apparatus for providing data transfer control 有权
公开(公告)号：US07627698B2
公开(公告)日：2009-12-01
申请号：US11830448
申请日：2007-07-30
申请人： Edwin Franklin Barry , Edward A. Wolff
发明人： Edwin Franklin Barry , Edward A. Wolff
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.

26. 发明授权

US07302504B2 Methods and apparatus for providing data transfer control 有权
标题翻译：提供数据传输控制的方法和装置
公开(公告)号：US07302504B2
公开(公告)日：2007-11-27
申请号：US11533897
申请日：2006-09-21
申请人： Edwin Franklin Barry , Edward A. Wolff
发明人： Edwin Franklin Barry , Edward A. Wolff
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.
摘要翻译：描述了用于在数据处理系统内改进数据传输控制的各种有利机制。描述了一种DMA控制器，其被实现为支持多个传输控制器的多处理传输引擎，其可以独立地或协作地执行数据传输，每个传输控制器充当自主处理器，将DMA指令提取并分派给多个执行单元。特别地，提供了用于启动和控制数据传输序列的机制，以及自动获取被顺序解码但并行执行的DMA指令的过程。每个传输控制器内的双传送执行单元与独立的传输计数器一起被用于允许源和目标地址生成的解耦，并允许一个传送执行单元中的多个传输指令与另一个传输中的单个传输指令并行操作单元。通过使用特殊信号量操作，信号和消息同步，可以使用SIGNAL和WAIT类型指令明确地调用，或者通过使用特殊的“事件动作”寄存器来隐式地调用源和目标之间的数据流改进。还描述了可以协作执行“DMA到DMA”传输的传输控制器。传输控制器可以使用消息级同步来相互同步。

27. 发明授权

US07130934B2 Methods and apparatus for providing data transfer control 有权
公开(公告)号：US07130934B2
公开(公告)日：2006-10-31
申请号：US11100697
申请日：2005-04-07
申请人： Edwin Franklin Barry , Edward A. Wolff
发明人： Edwin Franklin Barry , Edward A. Wolff
IPC分类号： G06F13/00
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.

28. 发明授权

US06912608B2 Methods and apparatus for pipelined bus 有权
标题翻译：流水线总线的方法和装置
公开(公告)号：US06912608B2
公开(公告)日：2005-06-28
申请号：US10131941
申请日：2002-04-25
申请人： Edward A. Wolff , David Baker , Bryan Garnett Cope , Edwin Franklin Barry
发明人： Edward A. Wolff , David Baker , Bryan Garnett Cope , Edwin Franklin Barry
IPC分类号： G06F15/80 , G06F13/00
CPC分类号： G06F15/8007
摘要： Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a robust interconnected bus employing a scalable, pipelined, multi-client topology, with a fully synchronous, packet-switched, split-transaction data transfer model. Multiple non-interfering transfers may occur concurrently since there is no single point of contention on the bus. An aggressive packet transfer model with local conflict resolution in each client and packet-level retries allows recovery from collisions and buffer backups. Clients are assigned unique IDs, based upon a mapping from the system address space allowing identification needed for quick routing of packets among clients.
摘要翻译：用于流水线总线的技术，其为诸如处理元件，主机接口，存储器控制器和其他特定于应用的协处理器和外部接口单元的计算元件提供非常高的性能接口。流水线总线是一种强大的互连总线，采用可扩展的，流水线式的多客户端拓扑，具有完全同步的分组交换，分组交易数据传输模型。多个非干扰传输可能同时发生，因为总线上没有单一的争用点。在每个客户端和数据包级重试中，具有本地冲突解决能力的攻击性数据包传输模型允许从冲突和缓冲备份恢复。基于从系统地址空间的映射，客户端被分配唯一的ID，允许在客户端之间快速路由分组所需的标识。

29. 发明授权

US07836317B2 Methods and apparatus for power control in a scalable array of processor elements 有权
标题翻译：处理器元件可扩展阵列中功率控制的方法和装置
公开(公告)号：US07836317B2
公开(公告)日：2010-11-16
申请号：US12021538
申请日：2008-01-29
申请人： Patrick R. Marchand , Gerald George Pechanek , Edward A. Wolff
发明人： Patrick R. Marchand , Gerald George Pechanek , Edward A. Wolff
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30036 , G06F9/30079 , G06F9/30083 , G06F9/3012 , G06F9/30141 , G06F9/3853 , G06F9/3885 , Y02D10/128 , Y02D10/171
摘要： Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.
摘要翻译：在可扩展数组间接VLIW处理器中提供低功耗架构特性和技术。这些特征和技术包括可重配置寄存器文件的功率控制，多周期操作的条件功率控制和间接VLIW利用，以及使用ManArray寄存器文件索引机制的基于VLIW的向量处理的功率控制。这些技术适用于所有处理元件（PE）和阵列控制器序列处理器（SP），以提供显着的功率节省。

30. 发明授权

US07263624B2 Methods and apparatus for power control in a scalable array of processor elements 有权
标题翻译：处理器元件可扩展阵列中功率控制的方法和装置
公开(公告)号：US07263624B2
公开(公告)日：2007-08-28
申请号：US11128742
申请日：2005-05-13
申请人： Patrick R. Marchand , Gerald George Pechanek , Edward A. Wolff
发明人： Patrick R. Marchand , Gerald George Pechanek , Edward A. Wolff
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F9/30036 , G06F9/30101 , G06F9/3853 , G06F9/3885 , G06F9/3891 , Y02D10/128
摘要： Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.
摘要翻译：在可扩展数组间接VLIW处理器中提供低功耗架构特性和技术。这些特征和技术包括可重配置寄存器文件的功率控制，多周期操作的条件功率控制和间接VLIW利用，以及使用ManArray寄存器文件索引机制的基于VLIW的向量处理的功率控制。这些技术适用于所有处理元件（PE）和阵列控制器序列处理器（SP），以提供显着的功率节省。

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