专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20110153890A1 Methods and Apparatus for Providing Data Transfer Control 有权
标题翻译：提供数据传输控制的方法和装置
公开(公告)号：US20110153890A1
公开(公告)日：2011-06-23
申请号：US13037619
申请日：2011-03-01
申请人： Edwin Frank Barry , Edward A. Wolff
发明人： Edwin Frank Barry , Edward A. Wolff
IPC分类号： G06F13/00
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.
摘要翻译：描述了用于在数据处理系统内改进数据传输控制的各种有利机制。描述了一种DMA控制器，其被实现为支持多个传输控制器的多处理传输引擎，其可以独立地或协作地执行数据传输，每个传输控制器充当自治处理器，将DMA指令提取并分派给多个执行单元。特别地，提供了用于启动和控制数据传输序列的机制，以及自动获取被顺序解码但并行执行的DMA指令的过程。每个传输控制器内的双传送执行单元与独立的传输计数器一起被用于允许源和目标地址生成的解耦，并允许一个传送执行单元中的多个传输指令与另一个传输中的单个传输指令并行操作单元。通过使用特殊信号量操作，信号和消息同步，可以使用SIGNAL和WAIT类型指令明确地调用，或者通过使用特殊的“事件动作”寄存器来隐式地调用源和目标之间的数据流改进。还描述了可以协作执行“DMA到DMA”传输的传输控制器。传输控制器可以使用消息级同步来相互同步。

22. 发明授权

US06721822B2 Methods and apparatus for providing data transfer control 有权
标题翻译：提供数据传输控制的方法和装置
公开(公告)号：US06721822B2
公开(公告)日：2004-04-13
申请号：US10254105
申请日：2002-09-24
申请人： Edwin Frank Barry , Edward A. Wolff
发明人： Edwin Frank Barry , Edward A. Wolff
IPC分类号： G06F1300
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.
摘要翻译：描述了用于在数据处理系统内改进数据传输控制的各种有利机制。描述了一种DMA控制器，其被实现为支持多个传输控制器的多处理传输引擎，其可以独立地或协作地执行数据传输，每个传输控制器充当自治处理器，将DMA指令提取并分派给多个执行单元。特别地，提供了用于启动和控制数据传输序列的机制，以及自动获取被顺序解码但并行执行的DMA指令的过程。每个传输控制器内的双传送执行单元与独立的传输计数器一起被用于允许源和目标地址生成的解耦，并允许一个传送执行单元中的多个传输指令与另一个传输中的单个传输指令并行操作单元。通过使用特殊信号量操作，信号和消息同步，可以使用SIGNAL和WAIT类型指令明确地调用，或者通过使用特殊的“事件动作”寄存器来隐式地调用源和目标之间的数据流改进。还描述了可以协作执行“DMA到DMA”传输的传输控制器。传输控制器可以使用消息级同步来相互同步。

23. 发明授权

US06260082B1 Methods and apparatus for providing data transfer control 有权
标题翻译：提供数据传输控制的方法和装置
公开(公告)号：US06260082B1
公开(公告)日：2001-07-10
申请号：US09471217
申请日：1999-12-23
申请人： Edwin Frank Barry , Edward A. Wolff
发明人： Edwin Frank Barry , Edward A. Wolff
IPC分类号： G06F1300
CPC分类号： G06F13/126 , G06F13/28
摘要： A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.
摘要翻译：描述了用于在数据处理系统内改进数据传输控制的各种有利机制。描述了一种DMA控制器，其被实现为支持多个传输控制器的多处理传输引擎，其可以独立地或协作地执行数据传输，每个传输控制器充当自治处理器，将DMA指令提取并分派给多个执行单元。特别地，提供了用于启动和控制数据传输序列的机制，以及自动获取被顺序解码但并行执行的DMA指令的过程。每个传输控制器内的双传送执行单元与独立的传输计数器一起被用于允许源和目标地址生成的解耦，并允许一个传送执行单元中的多个传输指令与另一个传输中的单个传输指令并行操作单元。通过使用特殊信号量操作，信号和消息同步，可以使用SIGNAL和WAIT类型指令明确地调用，或者通过使用特殊的“事件动作”寄存器来隐式地调用源和目标之间的数据流改进。还描述了可以协作执行“DMA到DMA”传输的传输控制器。传输控制器可以使用消息级同步来相互同步。

24. 发明授权

US06453367B2 Methods and apparatus for providing direct memory access control 有权
标题翻译：提供直接存储器访问控制的方法和装置
公开(公告)号：US06453367B2
公开(公告)日：2002-09-17
申请号：US09854789
申请日：2001-05-14
申请人： Edwin Frank Barry
发明人： Edwin Frank Barry
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array (ManArray) processing system employing an array of processing elements. Virtual to physical processing element (PE) identifier translation is employed in conjunction with a ManArray PE interconnection topology to support a variety of communication models, such as hypercube and such. Also, PE addressing nodes are based upon logically nested parameterized loops. Mechanisms for updating loop parameters, as well as exemplary instruction formats are also described.
摘要翻译：描述了用于提供数据分配机制和数据处理系统中来自多个存储器的数据收集的技术。该系统可以适当地是采用处理元件阵列的歧管阵列（ManArray）处理系统。虚拟到物理处理元素（PE）标识符转换与ManArray PE互连拓扑结合使用，以支持各种通信模型，例如超立方体等。此外，PE寻址节点基于逻辑嵌套的参数化循环。还描述了更新循环参数的机制以及示例性指令格式。

25. 发明授权

US06256683B1 Methods and apparatus for providing direct memory access control 有权
标题翻译：提供直接存储器访问控制的方法和装置
公开(公告)号：US06256683B1
公开(公告)日：2001-07-03
申请号：US09472372
申请日：1999-12-23
申请人： Edwin Frank Barry
发明人： Edwin Frank Barry
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array (ManArray) processing system employing an array of processing elements. Virtual to physical processing element (PE) identifier translation is employed in conjunction with a ManArray PE interconnection topology to support a variety of communication models, such as hypercube and such. Also, PE addressing nodes are based upon logically nested parameterized loops. Mechanisms for updating loop parameters, as well as exemplary instruction formats are also described.
摘要翻译：描述了用于提供数据分配机制和数据处理系统中来自多个存储器的数据收集的技术。该系统可以适当地是采用处理元件阵列的歧管阵列（ManArray）处理系统。虚拟到物理处理元素（PE）标识符转换与ManArray PE互连拓扑结合使用，以支持各种通信模型，例如超立方体等。此外，PE寻址节点基于逻辑嵌套的参数化循环。还描述了更新循环参数的机制以及示例性指令格式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式