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21. 发明申请

US20150378841A1 Techniques to Communicate with a Controller for a Non-Volatile Dual In-Line Memory Module 有权
标题翻译：与非易失性双列直插式存储器模块的控制器进行通信的技术
公开(公告)号：US20150378841A1
公开(公告)日：2015-12-31
申请号：US14319361
申请日：2014-06-30
申请人： Sarathy Jayakumar , Mohan J. Kumar , Adam J. Brooks , George Vergis
发明人： Sarathy Jayakumar , Mohan J. Kumar , Adam J. Brooks , George Vergis
IPC分类号： G06F11/14 , G06F3/06 , G11C14/00 , G06F9/44
CPC分类号： G06F9/4401 , G06F11/1441 , G06F11/2015
摘要： Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.
摘要翻译：示例可以包括通过系统管理总线（SMBus）接口与用于非易失性双列直插存储器模块的控制器进行通信。在一些示例中，通过SMBus接口可访问的寄存器中保持的位的选择性断言可以实现与控制器的通信。选择性断言可以基于寄存器映射。

22. 发明申请

US20130003468A1 MEMORY MODULE BUS TERMINATION VOLTAGE (VTT) REGULATION AND MANAGEMENT 有权
标题翻译：存储模块总线终端电压（VTT）规范和管理
公开(公告)号：US20130003468A1
公开(公告)日：2013-01-03
申请号：US13172795
申请日：2011-06-29
申请人： George Vergis
发明人： George Vergis
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1063
摘要： Embodiments of the present disclosure describe memory module bus termination voltage (VTT) regulation and management techniques and configurations. A method includes receiving, by a register, a signal that is driven over a bus to a memory device comprising a plurality of memory cells and setting, within the register, a termination voltage (VTT) for the bus based on the signal. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了存储器模块总线终端电压（VTT）调节和管理技术和配置。一种方法包括通过寄存器将通过总线驱动的信号接收到包括多个存储器单元的存储器件，并且根据该信号在寄存器内设置总线的终端电压（VTT）。可以描述和/或要求保护其他实施例。

23. 发明申请

US20100141501A1 CODESET COMMUNICATION FORMAT AND RELATED METHODS AND STRUCTURES 有权
标题翻译：编码通信格式及相关方法和结构
公开(公告)号：US20100141501A1
公开(公告)日：2010-06-10
申请号：US12706080
申请日：2010-02-16
申请人： George Vergis
发明人： George Vergis
IPC分类号： H04L17/02
CPC分类号： G08C23/04 , G08C19/28 , H04N5/4403 , H04N2005/4426
摘要： A codeset is described in a Public Codeset Communication Format (PCCF) as a format block including a plurality of fields having readily decipherable values, such as ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability.
摘要翻译：代码集以公共编码集通信格式（PCCF）描述为格式块，其包括具有易于解密的值的多个字段，例如ASCII字符值。一个字段是标记/空间信息字段，其包括用于代码集的操作信号的标记时间指示符和空间时间指示符的序列。第二场是用于操作信号的信号特征信息场。信号特征信息可以包括载波开/关信息，重复帧信息，切换控制信息和最后帧信息。 PCCF是一般适用性的代码集交换格式。

24. 发明授权

US07307900B2 Method and apparatus for optimizing strobe to clock relationship 有权
标题翻译：用于优化频闪到时钟关系的方法和装置
公开(公告)号：US07307900B2
公开(公告)日：2007-12-11
申请号：US11001554
申请日：2004-11-30
申请人： Joe Salmon , Navneet Dour , George Vergis
发明人： Joe Salmon , Navneet Dour , George Vergis
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00 , G11C8/18 , G06F13/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or retards the clock to DQS at the memory controller hub (MCH) to achieve the proper DRAM relationship. In one embodiment, the memory controller advances DQS if a binary zero value is read. In contrast, the memory controller retards DQS if a binary one value is read.
摘要翻译：为了允许存储器控制器将选通脉冲与DRAM的时钟关系同步，诸如触发器的寄存器被并入DRAM内以便于利用DQS对SCLK进行采样。同样，当DRAM处于测试操作模式时，存储器控制器将时钟提前或延迟到存储器控制器集线器（MCH）处的DQS以实现适当的DRAM关系。在一个实施例中，如果读取二进制零值，则存储器控制器提前DQS。相比之下，如果读取二进制一个值，则内存控制器会阻止DQS。

25. 发明申请

US20070126463A1 Polarity driven dynamic on-die termination 有权
标题翻译：极性驱动动态片上终端
公开(公告)号：US20070126463A1
公开(公告)日：2007-06-07
申请号：US11296950
申请日：2005-12-07
申请人： Christopher Cox , George Vergis , Hany Fahmy , Hideo Oie
发明人： Christopher Cox , George Vergis , Hany Fahmy , Hideo Oie
IPC分类号： H03K19/003
CPC分类号： G11C29/02 , G11C5/063 , G11C5/066 , G11C7/1048 , G11C7/20 , G11C29/025 , G11C29/028 , G11C29/50008
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further include control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于极性驱动的片上端接的系统，方法和装置。在一些实施例中，集成电路包括用于接收命令的输入/输出（I / O）电路和用于接收一个或多个ODT信号的片上终端（ODT）引脚。集成电路还可以包括耦合到ODT引脚的控制逻辑，所述控制逻辑至少部分地使得ODT引脚上的ODT激活信号和ODT值选择信号的复用，所述控制逻辑进一步控制至少部分地基于命令的长度。描述和要求保护其他实施例。

26. 发明授权

US08761199B2 Codeset communication format and related methods and structures 有权
标题翻译：编码通信格式及相关方法和结构
公开(公告)号：US08761199B2
公开(公告)日：2014-06-24
申请号：US12706080
申请日：2010-02-16
申请人： George Vergis
发明人： George Vergis
IPC分类号： H04J3/16
CPC分类号： G08C23/04 , G08C19/28 , H04N5/4403 , H04N2005/4426
摘要： A codeset is described in a Public Codeset Communication Format (PCCF) as a format block including a plurality of fields having readily decipherable values, such as ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability.
摘要翻译：代码集以公共编码集通信格式（PCCF）描述为格式块，其包括具有易于解密的值的多个字段，例如ASCII字符值。一个字段是标记/空间信息字段，其包括用于代码集的操作信号的标记时间指示符和空间时间指示符的序列。第二场是用于操作信号的信号特征信息场。信号特征信息可以包括载波开/关信息，重复帧信息，切换控制信息和最后帧信息。 PCCF是一般适用性的代码集交换格式。

27. 发明授权

US07889112B1 Dynamic linking of codesets in universal remote control devices 有权
标题翻译：通用遥控设备中代码集的动态链接
公开(公告)号：US07889112B1
公开(公告)日：2011-02-15
申请号：US11655419
申请日：2007-01-19
申请人： George Vergis , Sunilkumar Mankame
发明人： George Vergis , Sunilkumar Mankame
IPC分类号： H04L17/02
CPC分类号： H04N5/4403 , G08C17/02 , G08C19/28 , G08C19/36 , G08C2201/20 , H04N21/42225
摘要： A universal remote control device does not include a particular codeset that contains all the keycodes corresponding to all desired functions of a selected consumer electronic device. However, keycodes contained in one codeset in combination with keycodes contained in another codeset correspond to all desired functions of the selected electronic consumer device. A user presses a predefined sequence of keys to link the two codesets. A keycode link routine generates keycode link information and stores the keycode link information in a volatile memory space. The linked codeset is then used to control the selected electronic consumer device. Thereafter, pressing a first key causes a keycode in the first codeset to be used in generating an operational signal, whereas pressing a second key causes the keycode link information to be used to access a keycode in a second codeset such that the second keycode is used in generating the operational signal.
摘要翻译：通用遥控设备不包括包含对应于所选择的消费电子设备的所有所需功能的所有键码的特定代码集。然而，包含在一个代码集中的键码与其他代码集中包含的键码组合在一起对应于所选择的电子消费者设备的所有所需功能。用户按预定义的键序列来链接两个代码集。键码链接例程产生键码链接信息，并将键码链接信息存储在易失性存储器空间中。然后将链接的代码集用于控制所选择的电子消费者设备。此后，按下第一键使第一代码集中的键码用于产生操作信号，而按下第二键使得键码链接信息用于访问第二代码集中的键码，使得使用第二键码在产生操作信号。

28. 发明授权

US07668197B1 Codeset communication format and related methods and structures 有权
标题翻译：编码通信格式及相关方法和结构
公开(公告)号：US07668197B1
公开(公告)日：2010-02-23
申请号：US11359149
申请日：2006-02-21
申请人： George Vergis
发明人： George Vergis
IPC分类号： H04J3/16 , H04J3/22
CPC分类号： G08C23/04 , G08C19/28 , H04N5/4403 , H04N2005/4426
摘要： A codeset is described in a Public Codeset Communication Format (PCCF) as a format block. The format block includes a plurality of readily decipherable fields of ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability. In one method, a second entity describes a codeset in the PCCF format and then communicates the PCCF format information to a second entity. The second entity converts the information into a format usable by a rendering engine. The rendering engine is then usable to generate operational signals of the codeset.
摘要翻译：代码集以公共编码通信格式（PCCF）描述为格式块。格式块包括多个易于解密的ASCII字符值的字段。一个字段是标记/空间信息字段，其包括用于代码集的操作信号的标记时间指示符和空间时间指示符的序列。第二场是用于操作信号的信号特征信息场。信号特征信息可以包括载波开/关信息，重复帧信息，切换控制信息和最后帧信息。 PCCF是一般适用性的代码集交换格式。在一种方法中，第二实体描述PCCF格式的代码集，然后将PCCF格式信息传送给第二实体。第二实体将信息转换成可由渲染引擎使用的格式。渲染引擎然后可用于生成代码集的操作信号。

29. 发明申请

US20070247185A1 Memory system with dynamic termination 审中-公开
标题翻译：内存系统动态终止
公开(公告)号：US20070247185A1
公开(公告)日：2007-10-25
申请号：US11396277
申请日：2006-03-30
申请人： Hideo Oie , Hany Fahmy , Christopher Cox , George Vergis
发明人： Hideo Oie , Hany Fahmy , Christopher Cox , George Vergis
IPC分类号： H03K19/003
CPC分类号： H04L25/0298 , H04L25/0278
摘要： The termination impedance of a memory agent may be selected dynamically. A transmission line may be simultaneously terminated with a first impedance at first memory agent and a different impedance at a second memory agent. A memory agent may have a terminator with at least two termination values and logic to dynamically select the termination values. Other embodiments are described and claimed.
摘要翻译：可以动态地选择存储器的终止阻抗。传输线可以以第一存储器处的第一阻抗和第二存储器处的不同阻抗同时终止。存储器可以具有终止器，其具有至少两个终止值和逻辑以动态地选择终止值。描述和要求保护其他实施例。

30. 发明申请

US20190245309A1 CROSSTALK REDUCING CONNECTOR PIN GEOMETRY 审中-公开
公开(公告)号：US20190245309A1
公开(公告)日：2019-08-08
申请号：US16389781
申请日：2019-04-19
申请人： Jaejin Lee , Jun Liao , Xiang Li , George Vergis , Christopher E. Cox
发明人： Jaejin Lee , Jun Liao , Xiang Li , George Vergis , Christopher E. Cox
IPC分类号： H01R13/6471 , H05K5/00 , H05K5/02 , H05K1/18 , H01R12/73
CPC分类号： H01R13/6471 , H01R12/73 , H05K1/18 , H05K5/0069 , H05K5/0247 , H05K2201/10159 , H05K2201/10189
摘要： Embodiments of the present disclosure relate to a connector to connect a printed circuit board (PCB) with a memory device, where the connector includes a housing couplable with the PCB; a first signal pin coupled with the housing, where the first signal pin includes a first portion that includes a first curve, and a second portion that extends from the first portion and includes a second curve; and a second signal pin coupled with the housing, where the second signal pin includes a third portion that includes a third curve, and a fourth portion that extends from the third portion and includes a fourth curve, where the first curve is curved in a first opposite direction relative to the third curve, and where the second curve is curved in a second opposite direction relative to the fourth curve.

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