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21. 发明申请

US20090302298A1 Forming sublithographic phase change memory heaters 审中-公开
标题翻译：形成亚光刻相变记忆体加热器
公开(公告)号：US20090302298A1
公开(公告)日：2009-12-10
申请号：US12156851
申请日：2008-06-05
申请人： Jong-Won S. Lee , Gianpaolo Spadini
发明人： Jong-Won S. Lee , Gianpaolo Spadini
IPC分类号： H01L45/00 , H01L21/311
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/16 , H01L45/1675
摘要： A phase change memory may be formed with a sublithographic heater by using a mask with a sidewall spacer to etch an opening in a dielectric layer. The opening then has a sublithographic lateral extent. The resulting via may be filled with a heater material to form a sublithographic heater.
摘要翻译：可以用亚光刻加热器通过使用具有侧壁间隔物的掩模来蚀刻介电层中的开口来形成相变存储器。然后，开口具有亚光刻横向范围。所得到的通孔可以用加热器材料填充以形成亚光刻加热器。

22. 发明申请

US20090026437A1 Copper compatible chalcogenide phase change memory with adjustable threshold voltage 有权
标题翻译：铜兼容的硫族化物相变存储器，具有可调阈值电压
公开(公告)号：US20090026437A1
公开(公告)日：2009-01-29
申请号：US11881080
申请日：2007-07-25
申请人： Yudong Kim , Charles C. Kuo , Gianpaolo Spadini
发明人： Yudong Kim , Charles C. Kuo , Gianpaolo Spadini
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/24 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683
摘要： A phase change memory cell may include two or more stacked or unstacked series connected memory elements. The cell has a higher, adjustable threshold voltage. A copper diffusion plug may be provided within a pore over a copper line. By positioning the plug below the subsequent chalcogenide layer, the plug may be effective to block copper diffusion upwardly into the pore and into the chalcogenide material. Such diffusion may adversely affect the electrical characteristics of the chalcogenide layer.
摘要翻译：相变存储器单元可以包括两个或更多个堆叠或未堆叠的串联连接的存储器元件。电池具有更高的可调阈值电压。可以在铜线上的孔内提供铜扩散塞。通过将塞子放置在随后的硫族化物层之下，塞子可以有效地阻止铜扩散到孔中并进入硫族化物材料。这种扩散可能不利地影响硫族化物层的电特性。

23. 发明授权

US06504191B2 Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor 有权
公开(公告)号：US06504191B2
公开(公告)日：2003-01-07
申请号：US09972563
申请日：2001-10-08
申请人： Donald S. Gerber , Randy L. Yach , Kent D. Hewitt , Gianpaolo Spadini
发明人： Donald S. Gerber , Randy L. Yach , Kent D. Hewitt , Gianpaolo Spadini
IPC分类号： H01L2980
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/0207 , H01L27/11519
摘要： An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

24. 发明授权

US06219279B1 Non-volatile memory program driver and read reference circuits 有权
标题翻译：非易失性存储器程序驱动器和读取参考电路
公开(公告)号：US06219279B1
公开(公告)日：2001-04-17
申请号：US09430474
申请日：1999-10-29
申请人： Mihai Manolescu , Gianpaolo Spadini
发明人： Mihai Manolescu , Gianpaolo Spadini
IPC分类号： G11C1606
CPC分类号： G11C16/10 , G11C16/26
摘要： A method and circuits, in a non-volatile memory system such as EPROM, for limiting bit line current during programming that includes biasing a driving transistor to mirror a maximum desired current into the driving transistor from a mirroring transistor connected to a controlled current source. This technique is useful, for example, during hot electron programming of a floating gate memory cell to limit bit line current caused by snap back of the cell through which a relatively high current is passed. In a preferred embodiment, the state of a cell is monitored while being programmed by comparing the voltage of the bit line with a reference voltage that is developed in a circuit containing a replica of the driving transistor. Since characteristics of the driving and reference transistors are the same from wafer to wafer, or batch to batch, the reference voltage varies to compensate for variations in characteristics of the driving transistor among integrated circuit chips from different wafers and manufacturing batches.
摘要翻译：在诸如EPROM的非易失性存储器系统中的方法和电路，用于限制编程期间的位线电流，其包括偏置驱动晶体管以从连接到受控电流源的镜像晶体管镜像到驱动晶体管中的最大期望电流。该技术例如在浮动栅极存储器单元的热电子编程期间是有用的，以限制通过相对高的电流通过的单元的快速反应引起的位线电流。在优选实施例中，通过将位线的电压与在包含驱动晶体管的复制品的电路中产生的参考电压进行比较来编程监视单元的状态。由于驱动和参考晶体管的特性从晶圆到晶圆或批次相同，所以参考电压变化以补偿来自不同晶片和制造批次的集成电路芯片之间的驱动晶体管的特性的变化。

25. 发明授权

US09203024B2 Copper compatible chalcogenide phase change memory with adjustable threshold voltage 有权
公开(公告)号：US09203024B2
公开(公告)日：2015-12-01
申请号：US11881080
申请日：2007-07-25
申请人： Yudong Kim , Charles C. Kuo , Gianpaolo Spadini
发明人： Yudong Kim , Charles C. Kuo , Gianpaolo Spadini
IPC分类号： H01L21/00 , H01L21/06 , H01L45/00 , H01L27/24
CPC分类号： H01L45/144 , H01L27/24 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683
摘要： A phase change memory cell may include two or more stacked or unstacked series connected memory elements. The cell has a higher, adjustable threshold voltage. A copper diffusion plug may be provided within a pore over a copper line. By positioning the plug below the subsequent chalcogenide layer, the plug may be effective to block copper diffusion upwardly into the pore and into the chalcogenide material. Such diffusion may adversely affect the electrical characteristics of the chalcogenide layer.

26. 发明申请

US20130294152A1 APPARATUSES AND METHODS INCLUDING MEMORY ACCESS IN CROSS POINT MEMORY 有权
标题翻译：包含存储器访问的装置和方法在交叉点存储器中
公开(公告)号：US20130294152A1
公开(公告)日：2013-11-07
申请号：US13465579
申请日：2012-05-07
申请人： DerChang Kau , Gianpaolo Spadini
发明人： DerChang Kau , Gianpaolo Spadini
IPC分类号： G11C11/00 , H01L21/8239
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0097 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
摘要翻译：一些实施例包括具有存储器单元，被配置为访问存储单元的第一和第二导线以及被配置为向第一和第二导线中的一个施加信号的开关的装置和方法。在这样的实施例中的至少一个中，开关可以包括相变材料。描述包括附加装置和方法的其他实施例。

27. 发明授权

US08462537B2 Method and apparatus to reset a phase change memory and switch (PCMS) memory cell 有权
标题翻译：复位相变存储器和开关（PCMS）存储单元的方法和装置
公开(公告)号：US08462537B2
公开(公告)日：2013-06-11
申请号：US13052211
申请日：2011-03-21
申请人： Elijah V. Karpov , Gianpaolo Spadini
发明人： Elijah V. Karpov , Gianpaolo Spadini
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0076
摘要： The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, the non-volatile memory of the present disclosure may include a phase change memory and switch (hereinafter “PCMS”) memory cell and a process for resetting the PCMS memory utilizing a “look-up” table to calculate a current required to place a bit above a reference level to maximum threshold voltage.
摘要翻译：本公开涉及非易失性存储器件的制造。在至少一个实施例中，本公开的非易失性存储器可以包括相变存储器和开关（以下称为“PCMS”）存储器单元和利用“查找”表来重新计算PCMS存储器的过程，以计算将参考电平位置高于最大阈值电压所需的电流。

28. 发明授权

US08345472B2 Three-terminal ovonic threshold switch as a current driver in a phase change memory 有权
标题翻译：三端子超声门限开关作为相变存储器中的当前驱动器
公开(公告)号：US08345472B2
公开(公告)日：2013-01-01
申请号：US12974424
申请日：2010-12-21
申请人： Jong-Won Lee , Gianpaolo Spadini
发明人： Jong-Won Lee , Gianpaolo Spadini
IPC分类号： G11C11/00
CPC分类号： H01L45/1675 , G11C5/147 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/0069 , G11C2013/0092 , G11C2213/76 , H01L27/2436 , H01L45/00 , H01L45/04 , H01L45/1206 , H01L45/141
摘要： A three-terminal Ovonic Threshold Switch (OTS) is used to provide current to a Phase Change Memory Switch (PCMS) cross point array. The current is started by sending a small current into the second terminal of the three-terminal OTS allowing a larger current to flow from the first terminal to the third terminal of the three-terminal OTS. A method of making the three-terminal OTS is also presented.
摘要翻译：三端Ovonic阈值开关（OTS）用于向相变存储器开关（PCMS）交叉点阵列提供电流。通过向三端子OTS的第二端子发送小电流来开始电流，允许较大的电流从三端子OTS的第一端子流向第三端子。还提出了制作三端OTS的方法。

29. 发明申请

US20120294076A1 Forming Sublithographic Heaters for Phase Change Memories 有权
标题翻译：形成用于相变记忆片的亚光刻加热器
公开(公告)号：US20120294076A1
公开(公告)日：2012-11-22
申请号：US13564783
申请日：2012-08-02
申请人： Jong-Won S. Lee , Gianpaolo Spadini
发明人： Jong-Won S. Lee , Gianpaolo Spadini
IPC分类号： H01L47/00 , G11C11/21
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/1273 , H01L45/16
摘要： A phase change memory with a heater with sublithographic dimensions may be achieved, in some embodiments, with lower thermal budget. The phase change memory may use a controlled etching process to reduce the lateral dimension of the heater.
摘要翻译：具有亚光刻尺寸的加热器的相变存储器可以在一些实施例中具有较低的热量预算。相变存储器可以使用受控蚀刻工艺来减小加热器的横向尺寸。

30. 发明申请

US20110147695A1 FABRICATING CURRENT-CONFINING STRUCTURES IN PHASE CHANGE MEMORY SWITCH CELLS 有权
标题翻译：在相变记忆切换电池中制作电流结构
公开(公告)号：US20110147695A1
公开(公告)日：2011-06-23
申请号：US12646267
申请日：2009-12-23
申请人： Jong-Won Sean Lee , Derchang Kau , Gianpaolo Spadini
发明人： Jong-Won Sean Lee , Derchang Kau , Gianpaolo Spadini
IPC分类号： H01L45/00 , H01L21/36
CPC分类号： H01L45/1675 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.
摘要翻译：在一个或多个实施例中，提供了在相变存储器开关（PCMS）单元中制造电流限制堆叠结构的方法。一个实施例示出了制造具有限制在行和列方向上的上硫属化物中的电流的PCMS电池的方法。在一个实施例中，示出了制造具有亚光刻临界尺度存储硫族化物的PCMS单元的方法。在另一个实施例中，公开了制造具有亚光刻临界尺寸中间电极加热器的PCMS单元的方法。

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