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21. 发明授权

US5495122A Insulated-gate semiconductor field effect transistor which operates with a low gate voltage and high drain and source voltages 失效
标题翻译：绝缘栅半导体场效应晶体管以低栅极电压和高漏极和源极电压工作
公开(公告)号：US5495122A
公开(公告)日：1996-02-27
申请号：US246250
申请日：1994-05-19
申请人： Gen Tada
发明人： Gen Tada
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/76
CPC分类号： H01L27/088
摘要： In a low voltage drive circuit section of a semiconductor integrated circuit, the gate oxide films are approximately 250 .ANG., and a low voltage N-channel IGFET and a low voltage P-channel IGFET are operable at high speed and driven at a low voltage. In a high voltage driven circuit section, the gate oxide films are approximately 1500 .ANG., and a high voltage N-channel IGFET and a high voltage P-channel IGFET are designed to have a high breakdown voltage performance. In a low gate voltage/high voltage drive circuit section, the gate oxide films are approximately 250 .ANG., and a high voltage N-channel IGFET is driven at a low gate voltage and operable at high speed. The high voltage N-channel IGFET of the low gate voltage/high voltage drive circuit section has an offset structure including a drain diffusion layer of low concentration, such that the breakdown voltage of the drain is greatly increased.
摘要翻译：在半导体集成电路的低电压驱动电路部分中，栅极氧化物膜约为250安培，低电压N沟道IGFET和低电压P沟道IGFET可高速工作并以低电压驱动。在高电压驱动电路部分中，栅极氧化物膜约为1500安培，高压N沟道IGFET和高电压P沟道IGFET被设计成具有高的击穿电压性能。在低栅极电压/高压驱动电路部分中，栅极氧化物膜约为250安培，高电压N沟道IGFET以低栅极电压驱动并以高速运行。低栅极电压/高压驱动电路部分的高电压N沟道IGFET具有包括低浓度漏极扩散层的偏移结构，使得漏极的击穿电压大大增加。

22. 发明授权

US07876291B2 Drive device 失效
标题翻译：驱动装置
公开(公告)号：US07876291B2
公开(公告)日：2011-01-25
申请号：US11362517
申请日：2006-02-27
申请人： Hideto Kobayashi , Gen Tada , Yoshihiro Shigeta , Hiroshi Shimabukuro
发明人： Hideto Kobayashi , Gen Tada , Yoshihiro Shigeta , Hiroshi Shimabukuro
IPC分类号： G09G3/28
CPC分类号： G09G3/20 , G09G3/293 , G09G3/296 , G09G2310/0267
摘要： A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate and emitter of the IGBT, a buffer circuit, and a high side selector circuit including an inverter. The buffer circuit includes a high side Pch-MOS operated by a logic signal from the high side selector circuit and a low side Nch-MOS operated by a logic signal of the low side selector circuit.
摘要翻译：一种由电路元件占用的面积减小的显示面板驱动装置。显示面板驱动装置包括：输出级电路，具有通过串联连接反相器和缓冲电路构成的低侧选择电路，n沟道IGBT，齐纳二极管和分别连接在IGBT的栅极和发射极之间的电阻，缓冲器电路和包括逆变器的高侧选择器电路。缓冲电路包括由高侧选择器电路的逻辑信号操作的高边Pch-MOS和由低侧选择器电路的逻辑信号操作的低侧Nch-MOS。

23. 发明申请

US20060223254A1 Display panel drive device 失效
标题翻译：显示面板驱动装置
公开(公告)号：US20060223254A1
公开(公告)日：2006-10-05
申请号：US11362517
申请日：2006-02-27
申请人： Hideto Kobayashi , Gen Tada , Yoshihiro Shigeta , Hiroshi Shimabukuro
发明人： Hideto Kobayashi , Gen Tada , Yoshihiro Shigeta , Hiroshi Shimabukuro
IPC分类号： H01L21/8234
CPC分类号： G09G3/20 , G09G3/293 , G09G3/296 , G09G2310/0267
摘要： A display panel drive device of reduced area occupied by circuit elements. The display panel drive device includes an output stage circuit having a low side selector circuit constituted by connecting in series inverters and a buffer circuit, n-channel IGBTs, a Zener diode and resistance respectively connected between the gate and emitter of the IGBT, a buffer circuit, and a high side selector circuit including an inverter. The buffer circuit includes a high side Pch-MOS operated by a logic signal from the high side selector circuit and a low side Nch-MOS operated by a logic signal of the low side selector circuit.
摘要翻译：一种由电路元件占用的面积减小的显示面板驱动装置。显示面板驱动装置包括：输出级电路，具有通过串联连接反相器和缓冲电路构成的低侧选择电路，n沟道IGBT，齐纳二极管和分别连接在IGBT的栅极和发射极之间的电阻，缓冲器电路和包括逆变器的高侧选择器电路。缓冲电路包括由高侧选择器电路的逻辑信号操作的高边Pch-MOS和由低侧选择器电路的逻辑信号操作的低侧Nch-MOS。

24. 发明申请

US20050195179A1 Display device driver circuit 失效
标题翻译：显示设备驱动电路
公开(公告)号：US20050195179A1
公开(公告)日：2005-09-08
申请号：US11062780
申请日：2005-02-23
申请人： Hideto Kobayashi , Gen Tada , Yoshihiro Shigeta , Hiroshi Shimabukuro
发明人： Hideto Kobayashi , Gen Tada , Yoshihiro Shigeta , Hiroshi Shimabukuro
IPC分类号： G09G3/20 , G09F9/313 , G09G3/288 , G09G3/291 , G09G3/294 , G09G3/296 , G09G5/00 , H01J17/49 , H03K17/08 , H03K17/56 , H03K19/0185
CPC分类号： G09G3/296 , G09G2330/025 , G09G2330/04
摘要： A display device driver circuit includes a timer circuit 20 that outputs to output stage circuits 10 a control signal for turning off IGBTs 11 and 12 when a next clock signal is not inputted to the timer circuit 20 for a predetermined period of time, and the output stage circuits 10 turn off the IGBTs 11 and 12 to put the output terminals Do thereof into a high impedance state so that an overcurrent may be prevented from flowing through the IGBTs 11 and 12.
摘要翻译：显示装置驱动电路包括定时器电路20，其在下一个时钟信号未在定时器电路20输入预定时间段时向输出级电路10输出用于截止IGBT 11和12的控制信号，并且输出级电路10关断IGBT11和12，使其输出端子D 0进入高阻抗状态，从而可以防止过电流流过IGBT11和12。

25. 发明授权

US5545577A Method of producing a semiconductor device having two MIS transistor circuits 失效
标题翻译：制造具有两个MIS晶体管电路的半导体器件的方法
公开(公告)号：US5545577A
公开(公告)日：1996-08-13
申请号：US156847
申请日：1993-11-24
申请人： Gen Tada
发明人： Gen Tada
IPC分类号： H01L21/8234 , H01L27/088 , H01L27/092 , H01L21/70
CPC分类号： H01L27/0925
摘要： After forming a gate oxide film on the surface side of a single crystalline silicon substrate, a first polycrystalline silicon layer is subsequently formed. After that, portions of polycrystalline silicon layers are left in each gate electrode formation region of a high voltage drive circuit. Then, the gate oxide film in a low voltage drive circuit side is removed while maintaining this state. Then, after forming a gate oxide film on those surface sides, a polycrystalline silicon layer is subsequently formed in the surface side. After that, impurities are introduced into the polycrystalline silicon layer to provide it with electrical conduction, and then portions of polycrystalline silicon layers are left.
摘要翻译：在单晶硅衬底的表面侧形成栅极氧化膜之后，随后形成第一多晶硅层。之后，在高电压驱动电路的每个栅电极形成区域中留下多晶硅层的一部分。然后，在保持该状态的同时，去除低压驱动电路侧的栅极氧化膜。然后，在这些表面侧形成栅极氧化膜后，在表面侧随后形成多晶硅层。之后，将杂质引入多晶硅层以提供导电，然后留下多晶硅层的一部分。

26. 发明授权

US5497021A CMOS structure with varying gate oxide thickness and with both different and like conductivity-type gate electrodes 失效
标题翻译：制造具有两个误差晶体管电路的半导体器件的方法。
公开(公告)号：US5497021A
公开(公告)日：1996-03-05
申请号：US351569
申请日：1994-12-07
申请人： Gen Tada
发明人： Gen Tada
IPC分类号： H01L21/8234 , H01L27/088 , H01L27/092 , H01L29/94
CPC分类号： H01L27/0925
摘要： After forming a gate oxide film on the surface side of a single crystalline silicon substrate, a first polycrystalline silicon layer is subsequently formed. After that, portions of polycrystalline silicon layers are left in each gate electrode formation region of a high voltage drive circuit. Then, the gate oxide film in a low voltage drive circuit side is removed while maintaining this state. Then, after forming a gate oxide film on those surface sides, a polycrystalline silicon layer is subsequently formed in the surface side. After that, impurities are introduced into the polycrystalline silicon layer to provide it with electrical conduction, and then portions of polycrystalline silicon layers are left.
摘要翻译：在单晶硅衬底的表面侧形成栅极氧化膜之后，随后形成第一多晶硅层。之后，在高电压驱动电路的每个栅电极形成区域中留下多晶硅层的一部分。然后，在保持该状态的同时，去除低压驱动电路侧的栅极氧化膜。然后，在这些表面侧形成栅极氧化膜后，在表面侧随后形成多晶硅层。之后，将杂质引入多晶硅层以提供导电，然后留下多晶硅层的一部分。

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