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21. 发明申请

US20060267817A1 Using A Chip as a Simulation Engine 有权
公开(公告)号：US20060267817A1
公开(公告)日：2006-11-30
申请号：US11383541
申请日：2006-05-16
申请人： Gary Swoboda
发明人： Gary Swoboda
IPC分类号： H03M1/00
CPC分类号： G06F11/2268
摘要： The chip is placed in self simulation mode. When the trace logic does not have any more data to output it changes the state of the advance signal. The clock generator detects this state change and issues one gated clock to the functional logic. This creates a new CPU state and causes the change signal to toggle, and the trace logic notes the state change in the signal. It then exports the internal state presented to it. Once it completes the export, it changes the state of advance and the process begins anew.

22. 发明申请

US20060259822A1 PROFILING SYSTEM 有权
标题翻译：配置系统
公开(公告)号：US20060259822A1
公开(公告)日：2006-11-16
申请号：US11383370
申请日：2006-05-15
申请人： Gary Swoboda
发明人： Gary Swoboda
IPC分类号： G06F11/00
CPC分类号： G06F11/3636
摘要： A profiling system. At least some of the illustrative embodiments are integrated circuit devices comprising a processing circuit configured to execute a target program (the processing circuit having a plurality of registers), a trace system operatively coupled to the processing circuit (the trace system configured to collect trace data comprising the values of the plurality of registers, and the trace system configured to send the trace data for use by a debug program), a first memory operatively coupled to the processing circuit (the first memory comprising instructions to be executed by the processing circuit), and a memory location operatively coupled to the trace system (the memory location writable by the target program). The trace system is configured to send a value stored in the memory location to the host computer only when the value is newly written.
摘要翻译：分析系统。至少一些说明性实施例是集成电路设备，其包括被配置为执行目标程序（具有多个寄存器的处理电路）的处理电路，可操作地耦合到处理电路的跟踪系统（被配置为收集跟踪数据的跟踪系统包括多个寄存器的值，以及被配置为发送跟踪数据以供调试程序使用的跟踪系统），可操作地耦合到处理电路的第一存储器（包括由处理电路执行的指令的第一存储器）以及可操作地耦合到跟踪系统（由目标程序可写的存储器位置）的存储器位置。跟踪系统被配置为仅在新写入值时将存储在存储器位置中的值发送到主机计算机。

23. 发明申请

US20060259774A1 WATERMARK COUNTER WITH RELOAD REGISTER 审中-公开
标题翻译：带有RELOAD寄存器的WATERMARK计数器
公开(公告)号：US20060259774A1
公开(公告)日：2006-11-16
申请号：US11383464
申请日：2006-05-15
申请人： Gary Swoboda , Jason Peck
发明人： Gary Swoboda , Jason Peck
IPC分类号： H04L9/00
CPC分类号： G06F11/3648
摘要： A series of instructions from executable code are implemented on a processor core which in turn outputs event data. A watermark counter inputs event data and counts the number of events that occur within a time period defined by a start and stop signal. The watermark counter outputs a count value, corresponding to the number of events counted in the time period, across a connection to a monitoring computer.
摘要翻译：来自可执行代码的一系列指令在处理器核心上实现，该处理器核心又输出事件数据。水印计数器输入事件数据并对在由起始和停止信号定义的时间段内发生的事件数进行计数。水印计数器通过与监视计算机的连接输出与时间段中计数的事件数相对应的计数值。

24. 发明申请

US20060259162A1 EVENT AND STALL SELECTION 有权
标题翻译：活动和选举
公开(公告)号：US20060259162A1
公开(公告)日：2006-11-16
申请号：US11383389
申请日：2006-05-15
申请人： Gary Swoboda
发明人： Gary Swoboda
IPC分类号： G05B11/01
CPC分类号： G06F11/263
摘要： A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing logic partitioning the status signals into classes according to one or more user-specified partition criteria.
摘要翻译：一种方法，包括产生包括与硬件系统相关联的失速和事件信息的状态信号。该方法还包括根据一个或多个用户指定的分区标准将状态信号划分成类的多路复用逻辑。

25. 发明申请

US20060212760A1 System and method for sharing a communications link between multiple communications protocols 有权
标题翻译：用于共享多个通信协议之间的通信链路的系统和方法
公开(公告)号：US20060212760A1
公开(公告)日：2006-09-21
申请号：US11351443
申请日：2006-02-09
申请人： Gary Swoboda
发明人： Gary Swoboda
IPC分类号： G06F11/00
CPC分类号： G01R31/3177 , G01R31/31705 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318536 , G01R31/318544 , G01R31/318572
摘要： A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.
摘要翻译：描述了用于共享多个协议之间的通信链路的系统和方法，其包括：系统，其包括被配置为使用多个协议中的至少一个与其他系统交换信息的通信接口; 协议选择寄存器，其存储从所述多个协议之中选择协议以成为有效协议的值; 以及通信接口可访问的状态机，用于根据活动协议通过通信接口来控制信息交换的状态机。通信接口使用活动协议来交换信息，而多个协议的剩余协议保持不活动。状态机通过使通信接口根据活动协议进行操作的一系列状态进行排序，并在其余协议下被指定为惰性序列。

26. 发明申请

US20060156070A1 Locating and labeling device in a multi drop configuration 有权
标题翻译：在多点配置中定位和标注设备
公开(公告)号：US20060156070A1
公开(公告)日：2006-07-13
申请号：US11293599
申请日：2005-12-02
申请人： Gary Swoboda
发明人： Gary Swoboda
IPC分类号： G06F11/00
CPC分类号： G01R31/318544 , G01R31/31705 , G01R31/318536 , G01R31/318566
摘要： An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different among the target systems, outputting a bit from its bit pattern on the control signal. The process further comprises each target system comparing the resulting state of the control signal to that target system's output bit. If the target system's output bit differs from the resulting control signal state, the target system ceases participating in the ID process or, if the target system's output bit matches the resulting control signal state, the target system continues to participate in the ID process.
摘要翻译：识别（ID）处理包括在多个比特时间中的每一个中，调试测试系统将预定义状态的控制信号断言到多个目标系统，并且每个目标系统具有位模式并且位模式不同在目标系统中，从控制信号上的位模式输出一位。该过程还包括每个目标系统将控制信号的结果状态与该目标系统的输出位进行比较。如果目标系统的输出位与所得到的控制信号状态不同，则目标系统停止参与ID处理，或者如果目标系统的输出位与所得到的控制信号状态相匹配，则目标系统继续参与ID处理。

27. 发明申请

US20050166092A1 Emulation system with peripherals recording emulation frame when stop generated 有权
标题翻译：仿真系统与外设记录仿真帧停止时产生
公开(公告)号：US20050166092A1
公开(公告)日：2005-07-28
申请号：US11064242
申请日：2005-02-22
申请人： Gary Swoboda
发明人： Gary Swoboda
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： In-circuit-emulation of an integrated circuit includes a digital data processor capable of executing program instructions. A first debug event is detected during normal program execution. The causes the in-circuit-emulation to suspend program execution except for real time interrupts. A debug frame counter increments on each interrupt and decrements on each return from interrupt. If a debug event is detected during an interrupt service routine, that interrupt service routine is suspended and the count of the debug frame counter is stored. Execution of other interrupt service routines in response to corresponding interrupts is still permitted. The integrated circuit includes plural debug event detectors and the debug frame count is stored at the detector detecting a debug event during an interrupt service routine. This permits a determination of the order of interrupts triggering debug events by reading the stored debug frame count from each debug event detector.
摘要翻译：集成电路的在线仿真包括能够执行程序指令的数字数据处理器。在正常程序执行期间检测到第一个调试事件。导致在线仿真中断程序执行，除了实时中断。每个中断的调试帧计数器递增，每次从中断返回时递减。如果在中断服务程序期间检测到调试事件，则该中断服务程序被暂停，并且存储调试帧计数器的计数。仍然允许执行对应中断的其他中断服务程序。该集成电路包括多个调试事件检测器，并且调试帧计数被存储在检测器中，在中断服务程序期间检测调试事件。这允许通过从每个调试事件检测器读取存储的调试帧计数来确定触发调试事件的中断顺序。

28. 发明授权

US06775793B2 Data exchange system and method for processors 有权
标题翻译：数据交换系统和处理器的方法
公开(公告)号：US06775793B2
公开(公告)日：2004-08-10
申请号：US09738241
申请日：2000-12-15
申请人： Douglas Deao , Deborah Keil , Robert McGowan , Craig McLean , Gary Swoboda , Leland Szewerenko
发明人： Douglas Deao , Deborah Keil , Robert McGowan , Craig McLean , Gary Swoboda , Leland Szewerenko
IPC分类号： G06F1100
CPC分类号： G06F11/3652
摘要： A data exchange system that exchanges data between processors is provided. The system includes a host processor and a target processor. Data is exchanged by forming a data pipeline between the target processor and the host processor. The data pipeline includes a data unit on the target processor, an emulator and a device driver on the host processor. The data exchange system sends data through the data pipe line by transferring the data from a target memory on the target processor with the data unit to the emulator. The data exchange system transfers the data from the emulator to the first device driver.
摘要翻译：提供了一种在处理器之间交换数据的数据交换系统。该系统包括主处理器和目标处理器。通过在目标处理器和主处理器之间形成数据流水线来交换数据。数据流水线包括目标处理器上的数据单元，主处理器上的仿真器和设备驱动程序。数据交换系统通过数据管线将数据从数据单元的目标处理器上的目标存储器传送到仿真器，从而发送数据。数据交换系统将数据从仿真器传输到第一个设备驱动程序。

29. 发明授权

US08201004B2 Entry/exit control to/from a low power state in a complex multi level memory system 有权
标题翻译：在复杂的多级存储器系统中进/出控制低功率状态
公开(公告)号：US08201004B2
公开(公告)日：2012-06-12
申请号：US11855602
申请日：2007-09-14
申请人： Timothy David Anderson , Lewis Nardini , Jose Luis Flores , Abhijeet Chachad , Raguram Damodaran , Joseph R. M. Zbiciak , Gary Swoboda
发明人： Timothy David Anderson , Lewis Nardini , Jose Luis Flores , Abhijeet Chachad , Raguram Damodaran , Joseph R. M. Zbiciak , Gary Swoboda
IPC分类号： G06F1/04 , G06F1/10 , G06F1/18 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.
摘要翻译：嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。

30. 发明申请

US20110209015A1 SERIAL SCAN CHAIN IN A STAR CONFIGURATION 有权
标题翻译：星系配置中的串行扫描链
公开(公告)号：US20110209015A1
公开(公告)日：2011-08-25
申请号：US13098747
申请日：2011-05-02
申请人： Gary Swoboda
发明人： Gary Swoboda
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/318558
摘要： A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase.
摘要翻译：一种实现用于测试以星形配置耦合的多个组件的方法，每个组件具有测试接入端口（TAP）控制器。该方法包括在星形配置中对所有TAP控制器执行扫描操作的捕获阶段，并一次顺序地选择一个TAP控制器以执行移位状态。当所有TAP控制器已被顺序选择以执行移位阶段时，该方法还包括选择所有TAP控制器以执行更新阶段。

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