专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20050154901A1 Security measures in a partitionable computing system 有权
标题翻译：可分区计算系统中的安全措施
公开(公告)号：US20050154901A1
公开(公告)日：2005-07-14
申请号：US10756431
申请日：2004-01-12
申请人： Mark Shaw , Vipul Gandhi , Gary Gostin , Richard Powers , Guy Kuntz , Ryan Weaver
发明人： Mark Shaw , Vipul Gandhi , Gary Gostin , Richard Powers , Guy Kuntz , Ryan Weaver
IPC分类号： G06F21/00 , H04L9/32
CPC分类号： G06F21/53
摘要： Methods and apparatus in a partitionable computing system. The system can include a computer readable medium comprising instructions configured to move an element of a first partition to a second partition.
摘要翻译：可分区计算系统中的方法和装置。该系统可以包括计算机可读介质，其包括被配置为将第一分区的元素移动到第二分区的指令。

22. 发明授权

US09342452B2 Mapping processor address ranges to persistent storage 有权
标题翻译：将处理器地址范围映射到持久存储
公开(公告)号：US09342452B2
公开(公告)日：2016-05-17
申请号：US14349070
申请日：2011-10-07
申请人： Gary Gostin , Craig Warner , John W Bockhaus
发明人： Gary Gostin , Craig Warner , John W Bockhaus
IPC分类号： G06F12/02 , G06F12/08 , G06F12/06 , G06F13/16
CPC分类号： G06F12/0815 , G06F12/0223 , G06F12/06 , G06F12/0802 , G06F12/0873 , G06F12/10 , G06F13/16 , G06F2212/1024 , G06F2212/2024
摘要： A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.
摘要翻译：提供了一种用于访问存储的计算机装置和相关方法。在一个方面，控制器将存储器的数据块的地址范围映射到多个处理器中的至少一个处理器的可访问存储器地址范围。在另一方面，控制器确保由多个处理器缓存在多个存储器中的数据块的副本是一致的。

23. 发明申请

US20150081982A1 SHIELDING A MEMORY DEVICE 有权
标题翻译：屏蔽记忆设备
公开(公告)号：US20150081982A1
公开(公告)日：2015-03-19
申请号：US14387554
申请日：2012-04-27
申请人： Craig Warner , Gary Gostin , Matthew D. Pickett
发明人： Craig Warner , Gary Gostin , Matthew D. Pickett
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0833 , G06F12/0238 , G06F12/0866 , G06F12/122 , G06F13/1673 , G06F2212/1036 , G06F2212/312 , G06F2212/621 , G06F2212/7211
摘要： A method of shielding a memory device (110) from high write rates comprising receiving instructions to write data at a memory container (105), the memory controller (105) composing a cache (120) comprising a number of cache lines defining stored data, with the memory controller (105), updating a cache line in response to a write hit in the cache (120), and with the memory controller (105), executing the instruction to write data in response to a cache miss to a cache line within the cache (120) in which the memory controller (105) prioritizes for writing to the cache (120) over writing to the memory device (110).
摘要翻译：一种将存储器件（110）从高写入速率屏蔽的方法，包括接收在存储容器（105）上写入数据的指令，所述存储器控制器（105）构成包括定义存储数据的多条高速缓存行的高速缓存（120）利用存储器控制器（105），响应于高速缓存（120）中的写命中，以及与存储器控制器（105）一起更新高速缓存行，响应于高速缓存未命中将数据写入高速缓存行在所述存储器控制器（105）通过写入所述存储器件（110）的优先级来写入高速缓存（120）的高速缓存（120）内。

24. 发明授权

US08732331B2 Managing latencies in a multiprocessor interconnect 有权
标题翻译：管理多处理器互连中的延迟
公开(公告)号：US08732331B2
公开(公告)日：2014-05-20
申请号：US13122331
申请日：2008-10-02
申请人： Gregg B Lesartre , Craig Warner , Gary Gostin , John W Bockhaus
发明人： Gregg B Lesartre , Craig Warner , Gary Gostin , John W Bockhaus
IPC分类号： H04L12/801
CPC分类号： G06F15/173
摘要： In a computing system having a plurality of transaction source nodes issuing transactions into a switching fabric, an underserviced node notifies source nodes in the system that it needs additional system bandwidth to timely complete an ongoing transaction. The notified nodes continue to process already started transactions to completion, but stop the introduction of new traffic into the fabric until such time as the underserviced node indicates that it has progressed to a preselected point.
摘要翻译：在具有将事务发送到交换结构中的多个事务源节点的计算系统中，欠授权节点通知系统中的源节点需要额外的系统带宽以及时完成正在进行的事务。所通知的节点继续处理已经开始的事务完成，但是停止将新流量引入到结构中，直到欠观察节点指示它已经进展到预先选择的点为止。

25. 发明授权

US08539164B2 Cache coherency within multiprocessor computer system 有权
标题翻译：多处理器计算机系统中的缓存一致性
公开(公告)号：US08539164B2
公开(公告)日：2013-09-17
申请号：US12244700
申请日：2008-10-02
申请人： Craig Warner , Gary Gostin , Dan Robinson
发明人： Craig Warner , Gary Gostin , Dan Robinson
IPC分类号： G06F13/00
CPC分类号： G06F12/082 , G06F12/0831 , G06F12/12 , G06F2212/1048
摘要： An embodiment of a multiprocessor computer system comprises main memory, a remote processor capable of accessing the main memory, a remote cache device operative to store accesses by said remote processor to said main memory, and a filter tag cache device associated with the main memory. The filter cache device is operative to store information relating to remote ownership of data in the main memory including ownership by the remote processor. The filter cache device is operative to selectively invalidate filter tag cache entries when space is required in the filter tag cache device for new cache entries. The remote cache device is responsive to events indicating that a cache entry has low value to the remote processor to send a hint to the filter tag cache device. The filter tag cache device is responsive to a hint in selecting a filter tag cache entry to invalidate.
摘要翻译：多处理器计算机系统的实施例包括主存储器，能够访问主存储器的远程处理器，可操作以存储所述远程处理器对所述主存储器的访问的远程高速缓存设备以及与主存储器相关联的过滤器标签高速缓存设备。过滤器高速缓存设备用于存储与主存储器中的数据的远程所有权有关的信息，包括远程处理器的所有权。过滤器高速缓存设备可操作以在过滤器标签高速缓存设备中为新的高速缓存条目需要空间时，选择性地使过滤器标签高速缓存条目无效。远程高速缓存设备响应于指示高速缓存条目对于远程处理器具有低值以向该过滤器标签高速缓存设备发送提示的事件。过滤器标签缓存设备响应于选择过滤器标签高速缓存条目以使其无效的提示。

26. 发明申请

US20110179423A1 MANAGING LATENCIES IN A MULTIPROCESSOR INTERCONNECT 有权
标题翻译：在多处理器互连中管理延迟
公开(公告)号：US20110179423A1
公开(公告)日：2011-07-21
申请号：US13122331
申请日：2008-10-02
申请人： Gregg B. Lesartre , Craig Warner , Gary Gostin , John W. Bockhaus
发明人： Gregg B. Lesartre , Craig Warner , Gary Gostin , John W. Bockhaus
IPC分类号： G06F9/50
CPC分类号： G06F15/173
摘要： In a computing system having a plurality of transaction source nodes issuing transactions into a switching fabric, an underserviced node notifies source nodes in the system that it needs additional system bandwidth to timely complete an ongoing transaction. The notified nodes continue to process already started transactions to completion, but stop the introduction of new traffic into the fabric until such time as the underserviced node indicates that it has progressed to a preselected point.
摘要翻译：在具有将事务发送到交换结构中的多个事务源节点的计算系统中，欠授权节点通知系统中的源节点需要额外的系统带宽以及时完成正在进行的事务。所通知的节点继续处理已经开始的事务完成，但是停止将新流量引入到结构中，直到欠观察节点指示它已经进展到预先选择的点为止。

27. 发明申请

US20070180182A1 System and method for a distributed crossbar network using a plurality of crossbars 有权
标题翻译：一种使用多个十字条的分布式交叉网络的系统和方法
公开(公告)号：US20070180182A1
公开(公告)日：2007-08-02
申请号：US11346041
申请日：2006-02-02
申请人： Gary Gostin , Mark Shaw
发明人： Gary Gostin , Mark Shaw
IPC分类号： G06F13/00 , G06F15/76
CPC分类号： G06F13/4022 , G06F15/17337
摘要： A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the processors of one of the plurality of processor clusters to each of the processors of another of the plurality of processor clusters, such that all processors are coupled to each of the other processors, and such that the number of crossbars is equal to [X*(X−1)/2], wherein X equals the number of processor clusters.
摘要翻译：公开了一种用于多处理系统中的多跳交叉的单跳，处理器到处理器通信的系统和方法。简要描述，一个实施例是包括具有多个高带宽点对点链路的多个处理器的多处理系统; 多个处理器集群，每个处理器集群具有驻留在其中的预定数量的处理器; 以及多个十字条，所述十字条中的一个将所述多个处理器群中的一个处理器的处理器中的每一个耦合到所述多个处理器群中的另一处理器群的每个处理器，使得所有处理器耦合到每个其他处理器，并且使得十字形的数量等于[X *（X-1）/ 2]，其中X等于处理器集群的数量。

28. 发明申请

US20050198461A1 Security measures in a partitionable computing system 审中-公开
标题翻译：可分区计算系统中的安全措施
公开(公告)号：US20050198461A1
公开(公告)日：2005-09-08
申请号：US10756684
申请日：2004-01-12
申请人： Mark Shaw , Vipul Gandhi , Gary Gostin , Craig Wamer , Glen Edwards , Brian Johnson , Paul Bouchier
发明人： Mark Shaw , Vipul Gandhi , Gary Gostin , Craig Wamer , Glen Edwards , Brian Johnson , Paul Bouchier
IPC分类号： G06F12/16
CPC分类号： G06F11/3055 , G06F21/55 , G06F21/74
摘要： Methods and apparatus in a partitionable computing system. A state machine monitors the status of a partition or processor of the partitionable computing system. The state machine can include processor, a logic device, a register, and computer readable instructions.
摘要翻译：可分区计算系统中的方法和装置。状态机监视可分区计算系统的分区或处理器的状态。状态机可以包括处理器，逻辑设备，寄存器和计算机可读指令。

29. 发明申请

US20050152331A1 Security measures in a partitionable computing system 审中-公开
标题翻译：可分区计算系统中的安全措施
公开(公告)号：US20050152331A1
公开(公告)日：2005-07-14
申请号：US10756430
申请日：2004-01-12
申请人： Mark Shaw , Vipul Gandhi , Gary Gostin , Richard Powers
发明人： Mark Shaw , Vipul Gandhi , Gary Gostin , Richard Powers
IPC分类号： G06F13/00 , G06F21/00 , H04L12/28
CPC分类号： G06F21/50 , G06F21/74 , G06F2221/2105
摘要： Methods and apparatus in a partitionable computing system. A processor of a partition and a transmitter can configure and transmit a data packet that includes a source and a destination address. A routing device can have a port communication with the transmitter. The port can have a firewall associated therewith.
摘要翻译：可分区计算系统中的方法和装置。分区和发射机的处理器可以配置和发送包括源和目的地地址的数据分组。路由设备可以与发射机进行端口通信。该端口可以具有与之相关联的防火墙。

30. 发明申请

US20050154840A1 Cache line ownership transfer in multi-processor computer systems 失效
标题翻译：多处理器计算机系统中的高速缓存行所有权转移
公开(公告)号：US20050154840A1
公开(公告)日：2005-07-14
申请号：US10756436
申请日：2004-01-12
申请人： Christopher Greer , Michael Schroeder , Gary Gostin
发明人： Christopher Greer , Michael Schroeder , Gary Gostin
IPC分类号： G06F13/16 , G06F12/00 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0822 , Y10S707/99952
摘要： Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory unit. The memory unit receives the request and determines which one of a plurality of processors other than the requesting processor has ownership of the requested cache line. The memory sends an ownership recall to that processor. In response to the ownership recall, the other processor sends the requested cache line to the requesting processor, which may send a response to the memory unit to confirm receipt of the requested cache line. The other processor may optionally send a response to the memory unit to confirm that the other processor has sent the requested cache line to the requesting processor. A copy of the data for the requested cache line may, under some circumstances, also be sent to the memory unit by the other processor as part of the response.
摘要翻译：在共享内存多处理器计算机系统中的处理器之间传输高速缓存行所有权。高速缓存行的所有权请求从请求处理器发送到存储器单元。存储器单元接收该请求并确定除请求处理器之外的多个处理器中的哪一个处理器具有所请求的高速缓存行的所有权。内存向所述处理器发送所有权回收。响应于所有权调用，另一个处理器将请求的高速缓存行发送到请求处理器，该请求处理器可以向存储器单元发送响应以确认所请求的高速缓存行的接收。另一个处理器可以可选地向存储器单元发送响应以确认另一个处理器已将请求的高速缓存行发送到请求处理器。在某些情况下，所请求的高速缓存行的数据的副本也可以由其他处理器作为响应的一部分发送到存储器单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式