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21. 发明申请

US20130115755A1 METHOD OF SEPARATING SEMICONDUCTOR DIE USING MATERIAL MODIFICATION 有权
公开(公告)号：US20130115755A1
公开(公告)日：2013-05-09
申请号：US13359548
申请日：2012-01-27
申请人： Manfred Engelhardt , Petra Fischer
发明人： Manfred Engelhardt , Petra Fischer
IPC分类号： H01L21/78
CPC分类号： H01L21/78 , H01L21/3043 , H01L21/306 , H01L21/30604 , H01L21/3065 , H01L21/322 , H01L21/6835 , H01L21/6836 , H01L29/1608 , H01L2221/68327
摘要： A method for separating semiconductor die includes forming a porous region on a semiconductor wafer and separating the die at the porous region using mechanical or other means.

22. 发明申请

US20120322267A1 METHOD OF PATTERNING A SUBSTRATE 有权
标题翻译：图案化方法
公开(公告)号：US20120322267A1
公开(公告)日：2012-12-20
申请号：US13163792
申请日：2011-06-20
申请人： Manfred Engelhardt
发明人： Manfred Engelhardt
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/78 , H01L29/1608
摘要： In various embodiments, a method of patterning a substrate may include: forming an auxiliary layer on or above a substrate and forming a plasma etch mask layer on or above the auxiliary layer, wherein the auxiliary layer is configured such that it may be removed from the substrate more easily than the plasma etch mask layer; patterning the plasma etch mask layer and the auxiliary layer such that at least a portion of the substrate is exposed; patterning the substrate by means of a plasma etch process using the patterned plasma etch mask layer as a plasma etch mask.
摘要翻译：在各种实施例中，图案化衬底的方法可以包括：在衬底上或上方形成辅助层，并在辅助层上或上方形成等离子体蚀刻掩模层，其中辅助层被配置为使得其可以从衬底比等离子体蚀刻掩模层更容易; 图案化等离子体蚀刻掩模层和辅助层，使得至少一部分基板被暴露; 通过使用图案化等离子体蚀刻掩模层作为等离子体蚀刻掩模的等离子体蚀刻工艺图案化衬底。

23. 发明申请

US20080277760A1 INTEGRATED CIRCUIT DEVICE HAVING OPENINGS IN A LAYERED STRUCTURE 有权
标题翻译：具有层状结构的开口的集成电路装置
公开(公告)号：US20080277760A1
公开(公告)日：2008-11-13
申请号：US11744962
申请日：2007-05-07
申请人： Daniel Kohler , Manfred Engelhardt , Peter Baars , Hans-Peter Sperlich
发明人： Daniel Kohler , Manfred Engelhardt , Peter Baars , Hans-Peter Sperlich
IPC分类号： H01L29/00 , H01L21/28 , H01L21/311
CPC分类号： H01L28/91 , H01L21/31116 , H01L21/31144 , H01L21/76816 , H01L27/10855
摘要： An integrated circuit device includes a substrate with a first layer situated on the substrate. The first layer defines a first opening with a cover layer deposited on the first layer and coating a sidewall portion of the first opening. A second layer is situated on the cover layer. The second layer defines a second opening extending through the second layer and through the cover layer to connect the first and second openings.
摘要翻译：集成电路器件包括具有位于衬底上的第一层的衬底。第一层限定了具有沉积在第一层上并覆盖第一开口的侧壁部分的覆盖层的第一开口。第二层位于覆盖层上。第二层限定延伸穿过第二层并穿过覆盖层的第二开口以连接第一和第二开口。

24. 发明授权

US06946386B2 Process for producing ultrathin homogenous metal layers 有权
标题翻译：生产超薄均质金属层的方法
公开(公告)号：US06946386B2
公开(公告)日：2005-09-20
申请号：US10854759
申请日：2004-05-25
申请人： Gernot Steinlesberger , Manfred Engelhardt , Eugen Unger
发明人： Gernot Steinlesberger , Manfred Engelhardt , Eugen Unger
IPC分类号： C23C18/31 , C23C28/02 , H01L21/4763
CPC分类号： C23C18/31 , C23C28/023
摘要： A method of forming an ultrathin homogenous metal layer that serves as base metallization for formation of contact locations and/or contact pads and/or wirings of an integrated electronic component. The method includes the steps of depositing a first metal layer on a substrate at least in regions, and producing a second metal layer on the first metal layer at least in regions, component(s) of the second metal layer have a more positive redox potential than component(s) of the first metal layer, wherein ultrathin homogenous deposition of the second metal layer is effected by wet-chemical, current-free, electrochemical redox processes by element exchange from one or more metal salts as oxidant with at least a top metal atomic layer of the first metal layer as reductant.
摘要翻译：形成用于形成集成电子部件的接触位置和/或接触焊盘和/或布线的基底金属化的超薄均匀金属层的方法。该方法包括以下步骤：至少在区域中在衬底上沉积第一金属层，并且至少在区域中在第一金属层上产生第二金属层，第二金属层的组分具有更正的氧化还原电位其中第二金属层的超薄均匀沉积通过湿化学，无电流的电化学氧化还原过程通过元素交换从一种或多种金属盐作为氧化剂与至少一个顶部进行第一金属层的金属原子层作为还原剂。

25. 发明申请

US20050118342A1 Process for depositing a catalyst 审中-公开
标题翻译：沉积催化剂的方法
公开(公告)号：US20050118342A1
公开(公告)日：2005-06-02
申请号：US10980011
申请日：2004-11-03
申请人： Manfred Engelhardt , Gernot Steinlesberger , Eugen Unger
发明人： Manfred Engelhardt , Gernot Steinlesberger , Eugen Unger
IPC分类号： B01J23/745 , B01J23/755 , B01J37/03 , C01B31/02 , C23C18/16 , C23C18/31 , B05D3/02
CPC分类号： B82Y30/00 , B01J23/745 , B01J23/755 , B01J37/03 , B82Y40/00 , C01B32/162 , C23C18/161 , C23C18/54
摘要： A process for the selective and areal deposition of a catalyst is disclosed, which is intended for the growth of nanotubes, on an interconnect line in an integrated circuit or chip. The process includes providing an acidic or alkaline aqueous solution of the catalyst; applying the solution to the interconnect line; and removing the excess solution.
摘要翻译：公开了用于在集成电路或芯片的互连线上用于纳米管生长的选择性和面积沉积催化剂的方法。该方法包括提供催化剂的酸性或碱性水溶液; 将解决方案应用于互连线; 并除去多余的溶液。

26. 发明授权

US06387773B1 Method for fabricating trenches having hallows along the trenches side wall for storage capacitors of DRAM semiconductor memories 失效
标题翻译：用于制造具有沿着沟槽侧壁的具有用于DRAM半导体存储器的存储电容器的凹部的沟槽的方法
公开(公告)号：US06387773B1
公开(公告)日：2002-05-14
申请号：US09607355
申请日：2000-06-30
申请人： Manfred Engelhardt
发明人： Manfred Engelhardt
IPC分类号： H01L2120
CPC分类号： H01L27/1087
摘要： A method for fabricating trenches for storage capacitors of DRAM semiconductor memories by plasma etching semiconductor substrates, includes fabricating a partial trench region with a cross-sectional profile deviating from essentially constant toward a larger cross-sectional profile. A surface of the partial trench region is passivated and the etching/passivating step is continued periodically, in order to fabricate further partial trench regions, until a predetermined overall trench depth has been reached.
摘要翻译：通过等离子体蚀刻半导体衬底制造用于DRAM半导体存储器的存储电容器的沟槽的方法包括制造具有从基本上恒定的向较大横截面轮廓偏离的部分沟槽区域。部分沟槽区域的表面被钝化，并且蚀刻/钝化步骤周期性地继续，以便制造另外的部分沟槽区域，直到达到预定的整个沟槽深度。

27. 发明授权

US06210595B1 Method for producing structures having a high aspect ratio and structure having a high aspect ratio 有权
标题翻译：具有高纵横比和高纵横比的结构的结构的制造方法
公开(公告)号：US06210595B1
公开(公告)日：2001-04-03
申请号：US09149829
申请日：1998-09-08
申请人： Volker Weinrich , Manfred Engelhardt
发明人： Volker Weinrich , Manfred Engelhardt
IPC分类号： C23F100
CPC分类号： H01L27/10852 , C23F4/00 , H01L21/0335 , H01L21/32139 , H01L28/55 , H01L28/91
摘要： A method for producing structures having a high aspect ratio includes the following steps: a material of the structure to be produced is provided in the form of a layer, a mask is applied to the layer, the layer is subjected to dry etching using the mask, thereby forming redepositions of the layer material on side walls of the mask and the mask is removed, so that a structure having a high aspect ratio is left behind. The method enables very high (≧1 &mgr;m) and very thin (≦50 nm) structures to be produced in a relatively simple and rapid manner in only very few process steps and with only one mask technique. Structures having such large aspect ratios, particularly when they are composed of a conductive material, cannot be produced, or can be produced only with a high outlay, by using other methods.
摘要翻译：具有高纵横比的结构的制造方法包括以下步骤：以层的形式提供要制造的结构材料，将掩模施加到该层上，使用掩模进行干蚀刻，从而在掩模的侧壁上形成层材料的再沉积，并且去除掩模，使得留下具有高纵横比的结构。该方法使得非常高（> = 1mum）和非常薄（<= 50nm）的结构以相对简单和快速的方式仅在非常少的工艺步骤中产生，并且仅使用一种掩模技术。具有这样大的纵横比的结构，特别是当它们由导电材料组成时，不能通过使用其它方法产生，或者仅通过高成本制造。

28. 发明授权

US5118383A Method for producing trench structures in silicon substrates for VLSI semiconductor circuits 失效
标题翻译：用于生产VLSI半导体电路的硅衬底中的晶体结构的方法
公开(公告)号：US5118383A
公开(公告)日：1992-06-02
申请号：US636203
申请日：1990-12-31
申请人： Manfred Engelhardt
发明人： Manfred Engelhardt
IPC分类号： C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/76
CPC分类号： H01L21/3065
摘要： A method is provided for producing trench structures having vertical, smooth side walls and straight, flat trench floors in silicon substrates. The reactive ion etching is implemented in a triode single-wafer plate reactor upon use of an etching mask preferably composed of SiO.sub.2, and with an etching gas atmosphere exclusively composed of chlorine, being implemented at a low-pressure. Compared to known ion etching processes, the method provides acceptable etching rates with a carbon-free, simple etching chemistry. The method is particularly useful for producing DRAMs with cell concepts of more than 4 Mbits.
摘要翻译：提供了一种用于制造在硅衬底中具有垂直，平滑的侧壁和直的，平坦的沟槽地板的沟槽结构的方法。使用优选由SiO 2构成的蚀刻掩模和仅由氯构成的蚀刻气体气氛，在三极管单晶片板反应器中实施反应离子蚀刻，以低压实施。与已知的离子蚀刻工艺相比，该方法通过无碳，简单的刻蚀化学法提供可接受的蚀刻速率。该方法对于生产具有超过4Mbits的单元概念的DRAM特别有用。

29. 发明授权

US4283849A Cutting unit for a dry-shaving apparatus 失效
标题翻译：用于干燥剃须设备的切割单元
公开(公告)号：US4283849A
公开(公告)日：1981-08-18
申请号：US72277
申请日：1979-09-04
申请人： Manfred Engelhardt , Jan Reinink , Jochem J. de Vries , Eduard W. Tietjens
发明人： Manfred Engelhardt , Jan Reinink , Jochem J. de Vries , Eduard W. Tietjens
IPC分类号： B26B19/14 , B26B19/42
CPC分类号： B26B19/141 , B26B19/42
摘要： The movable cutting unit of a dry-shaver comprises a plurality of cutters (23) and a corresponding plurality of hair-pulling blades (24) each arranged in front of one of the cutters for movement therewith relative to the shear plate or foil of the shaver, and each movable relative to the associated cutter for its hair-pulling action. Each hair-pulling blade is mounted for pivoting motion on its associated cutter.
摘要翻译：干式剃须刀的可移动切割单元包括多个切割器（23）和相应的多个头发拉动叶片（24），每个切割器布置在一个切割器的前面，用于相对于剪切板或箔片剃须刀，并且每个剃须刀相对于相关联的切割器可移动以用于其牵引动作。每个拔毛刀被安装成在其相关联的切割器上枢转运动。

30. 发明授权

US09666452B2 Chip packages and methods for manufacturing a chip package 有权
公开(公告)号：US09666452B2
公开(公告)日：2017-05-30
申请号：US13480513
申请日：2012-05-25
申请人： Karl Adolf Dieter Mayer , Guenter Tutsch , Horst Theuss , Manfred Engelhardt , Joachim Mahler
发明人： Karl Adolf Dieter Mayer , Guenter Tutsch , Horst Theuss , Manfred Engelhardt , Joachim Mahler
IPC分类号： H01L21/44 , H01L21/00 , H01L21/56 , H01L23/00 , H01L21/78
CPC分类号： H01L21/561 , H01L21/78 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/94 , H01L2224/03002 , H01L2224/05009 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/0566 , H01L2224/05664 , H01L2224/05684 , H01L2224/06181 , H01L2224/49175 , H01L2224/92247 , H01L2224/94 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2224/03
摘要： A method for manufacturing a chip package is provided. The method including: holding a carrier including a plurality of dies; forming a separation between the plurality of dies by removing from the carrier one or more portions of the carrier between the plurality of dies; forming an encapsulation material in the removed one or more portions between the plurality of dies; separating the dies through the encapsulation material.

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