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21. 发明授权

US07075826B2 Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
公开(公告)号：US07075826B2
公开(公告)日：2006-07-11
申请号：US11036945
申请日：2005-01-14
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C16/06
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

22. 发明授权

US06862223B1 MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT 有权
标题翻译：单声道，组合非易失性存储器允许使用统一的单元结构和技术与解码器和布局的新方案在单元格阵列中无干扰和分离的字节，页面和块写入
公开(公告)号：US06862223B1
公开(公告)日：2005-03-01
申请号：US10223208
申请日：2002-08-19
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
IPC分类号： G11C11/34 , G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C11/005 , G11C16/0408 , G11C16/0416 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
摘要翻译：公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

23. 发明授权

US06777292B2 Set of three level concurrent word line bias conditions for a NOR type flash memory array 有权
公开(公告)号：US06777292B2
公开(公告)日：2004-08-17
申请号：US10627183
申请日：2003-07-25
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu , Mervyn Wong
IPC分类号： H01L21336
CPC分类号： G11C16/3404 , G11C16/0416 , G11C16/344 , H01L27/115 , H01L29/66825
摘要： In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value. The methods described herein produce a cell threshold voltage that has a narrow voltage distribution.

24. 发明授权

US06757196B1 Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device 有权
标题翻译：两个晶体管闪存单元，用于具有可编程逻辑器件的EEPROM阵列
公开(公告)号：US06757196B1
公开(公告)日：2004-06-29
申请号：US10016898
申请日：2001-12-14
申请人： Hsing-Ya Tsao , Peter W. Lee , Fu-Chang Hsu
发明人： Hsing-Ya Tsao , Peter W. Lee , Fu-Chang Hsu
IPC分类号： G11C1604
CPC分类号： G11C16/0433 , H01L27/115
摘要： The present invention describes a two transistor flash EEPROM memory cell which has a symmetrical source and drain structure, which permits the cell size not limited by program and erase operations. The memory cell comprises an NMOS floating gate transistor forming a nonvolatile storage device and an NMOS transistor forming an access device. The floating gate transistor is programmed and erased using Fowler-Nordheim channel tunneling. The two transistor memory cell is used in a memory array of columns and rows where a column of cells is coupled by a bit line and a source line, and where a row of cells is coupled by a word line and an access line. The memory array is highly scalable and is targeted for low-voltage, high-speed and high-density programmable logic devices.
摘要翻译：本发明描述了具有对称的源极和漏极结构的双晶体管快速EEPROM存储单元，这允许单元大小不受编程和擦除操作的限制。存储单元包括形成非易失性存储器件的NMOS浮栅晶体管和形成存取器件的NMOS晶体管。使用Fowler-Nordheim通道隧道对浮栅晶体管进行编程和擦除。两个晶体管存储单元用于列和行的存储器阵列中，其中一列单元由位线和源极线耦合，并且其中一行单元通过字线和存取线耦合。内存阵列具有高度可扩展性，适用于低电压，高速和高密度可编程逻辑器件。

25. 发明授权

US06628563B1 Flash memory array for multiple simultaneous operations 有权
标题翻译：闪存阵列用于多个同时操作
公开(公告)号：US06628563B1
公开(公告)日：2003-09-30
申请号：US10191228
申请日：2002-07-09
申请人： Fu-Chang Hsu , Peter W. Lee , Hsing-Ya Tsao
发明人： Fu-Chang Hsu , Peter W. Lee , Hsing-Ya Tsao
IPC分类号： G11C800
CPC分类号： G11C16/08 , G11C2216/22
摘要： A non-volatile integrated circuit memory having an AND-like array structure that is capable of simultaneous reading and writing of digital data to multiple memory cells within the integrated circuit memory has memory cells within an array block of memory cells are arranged in columns and rows. A plurality of block bit lines is in communication with each array block of memory cells such that each block bit line interconnects the memory cells of one column of memory cells within one array block. A plurality of word lines is in communication with each array block of memory cells such that each word line interconnects the memory cells of one row within one array block. The integrated circuit memory further includes a plurality of global bit lines in communication with the array blocks to select a column of the array blocks and to transfer the digital data from and to the array blocks. A bit line selector selectively connects the plurality of global bit lines to the block bit lines. An array controller controls selection of a row of a block of the array, control transfer of the digital data from selected global bit lines to selected block bit lines, control transfer of the digital data to other selected global bit lines from other selected bit lines to allow simultaneous transfer of the digital data from and to selected memory cells.
摘要翻译：具有AND状阵列结构的非易失性集成电路存储器能够同时读取和写入数字数据到集成电路存储器内的多个存储器单元，存储单元阵列块内的存储单元被排列成列和行。多个块位线与存储器单元的每个阵列块通信，使得每个块位线互连一个阵列块内的一列存储器单元的存储单元。多个字线与存储器单元的每个阵列块通信，使得每个字线互连一个阵列块内的一行的存储单元。集成电路存储器还包括与阵列块通信的多个全局位线，以选择阵列块的列并将数字数据从阵列块传送到阵列块。位线选择器有选择地将多个全局位线连接到块位线。阵列控制器控制对阵列的一行的选择，控制数字数据从所选择的全局位线传送到选择的块位线，控制数字数据从其它所选位线到其它所选择的全局位线的传送允许从选定的存储器单元同时传送数字数据。

26. 发明授权

US06515910B1 Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM 失效
标题翻译：非易失性半导体单晶体管单元，非型闪存EEPROM的逐位Vt校正操作
公开(公告)号：US06515910B1
公开(公告)日：2003-02-04
申请号：US10076826
申请日：2002-02-15
申请人： Peter W. Lee , Hsing-Ya Tsao , Tam Tran , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Tam Tran , Fu-Chang Hsu
IPC分类号： G11C1606
CPC分类号： G11C16/3409 , G11C16/3404 , G11C16/344 , G11C16/3445
摘要： A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under erase and over erase conditions. The erase condition of a section of the memory array device is altered to form an erased section and non-erased sections. The control gates of the memory cells in the non-erased sections are forced to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to a check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine erase condition of the selected subsection of the erase section.
摘要翻译：实现了对存储器阵列器件中的存储器单元的擦除条件进行测试的方法。该方法进一步扩展到在擦除和擦除条件下检测和校正的方法。存储器阵列器件的一部分的擦除条件被改变以形成擦除部分和非擦除部分。未擦除部分中的存储器单元的控制栅极被迫到足以关闭已擦除单元的正常截止状态电压。被擦除部分的未选择子部分中的存储器单元的控制栅极被强制为保证的关断状态电压，其将关闭包括那些被擦除的单元的擦除的单元。被擦除部分的选定子部分中的存储器单元的控制栅极被强制为检查电压。此后，测量擦除部分的所选子部分的位线电流，以确定擦除部分的所选子部分的擦除条件。

27. 发明授权

US06498752B1 Three step write process used for a nonvolatile NOR type EEPROM memory 有权
标题翻译：用于非易失性NOR型EEPROM存储器的三步写入过程
公开(公告)号：US06498752B1
公开(公告)日：2002-12-24
申请号：US09940159
申请日：2001-08-27
申请人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee
发明人： Fu-Chang Hsu , Hsing-Ya Tsao , Peter W. Lee
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/3459
摘要： The present invention discloses a novel method for erasing an ETOX type and an AND type NOR flash memory arrays. The operations of the methods includes block erase which increases the Vt of the memory cell, block erase verify to check if the Vt of the erased cell is greater than a predetermined voltage Vtoff, page reverse program which reduces the Vt of the memory cell below a predetermine voltage Vtmax, reverse program verify which checks that the Vt of the memory cell is below Vtmax, page correction which corrects the Vt of cells on a page basis to be above a predetermined voltage Vtmin, and correction verify which checks that the Vt of the memory cells is above Vtmin. According to the present invention, the erase operation is performed to increase the Vt of erased cells by applying the positive high voltages to the selected word lines with bit lines and source lines grounded. The reverse program operation is performed to decrease the Vt of erased cells by applying the negative high voltage to the selected word lines with the source lines and bit lines grounded. For the ETOX cell an FN tunneling scheme is utilized for the Erase operation and CHE for the correction operation. The AND cell uses FN tunneling for both erase and correction operations.
摘要翻译：本发明公开了一种用于擦除ETOX型和AND型NOR闪存阵列的新方法。方法的操作包括增加存储器单元的Vt的块擦除，块擦除验证以检查擦除单元的Vt是否大于预定电压Vtoff，页面反向程序，其将存储器单元的Vt减小到低于预先确定电压Vtmax，反向程序验证哪个检查存储器单元的Vt低于Vtmax，将页面上的单元格的Vt校正为高于预定电压Vtmin的页面校正，以及校正验证哪个检查Vt 存储单元高于Vtmin。根据本发明，执行擦除操作以通过将位线和源极线接地的正高电压施加到所选择的字线来增加擦除单元的Vt。执行反向编程操作以通过将源极线和位线接地来对所选择的字线施加负高电压来减小擦除单元的Vt。对于ETOX单元，使用FN隧道方案进行擦除操作和CHE进行校正操作。 AND单元使用FN隧道进行擦除和校正操作。

28. 发明授权

US06275417B1 Multiple level flash memory 有权
标题翻译：多级闪存
公开(公告)号：US06275417B1
公开(公告)日：2001-08-14
申请号：US09680651
申请日：2000-10-06
申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
发明人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao
IPC分类号： G11C1604
CPC分类号： G11C11/5642 , G11C7/06 , G11C11/5621 , G11C16/26 , G11C2211/5634
摘要： Data stored in multi-level memory cells is rapidly read out with high resolution by generating and coupling a predetermined and preferably low number of large magnitude jump-like voltage changes to the control gates of the memory cells. The magnitude of the jumps can be a substantial fraction of the power supply level and will be many times the &Dgr;Vt levels associated with the memory cells, e.g., the control gate voltage changes in jump-steps from say 4 V to 6 V to 8 V. Use of a low number of jump-steps (e.g., two or three) reduces read out time by permitting read out of a plurality of Vt levels during a given control voltage magnitude. Further, use of large but different magnitude control gate voltages provides good read out resolution over the range of Vt values. Reference cells are provided to improve tracking, and DRAM-type sense amplifiers are provided to maintain high noise immunity.
摘要翻译：存储在多电平存储单元中的数据通过产生并将预定的和优选的低数量的大幅度的类似跳变的电压变化耦合到存储器单元的控制栅极而以高分辨率快速读出。跳跃的幅度可以是电源电平的很大一部分，并且将是与存储器单元相关联的DELTAVt电平的许多倍，例如，控制栅极电压在从4V变为6V至8V的跳变步长使用低数量的跳跃步骤（例如，两个或三个）通过允许在给定的控制电压幅度期间读出多个Vt电平来减少读出时间。此外，使用大但不同幅度的栅极电压在Vt值的范围内提供良好的读出分辨率。提供参考单元以改善跟踪，并且提供DRAM型读出放大器以保持高抗噪声性。

29. 发明授权

US5848000A Flash memory address decoder with novel latch structure 失效
标题翻译：具有新型锁存结构的闪存地址解码器
公开(公告)号：US5848000A
公开(公告)日：1998-12-08
申请号：US819323
申请日：1997-03-18
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/10 , G11C8/12 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/3418 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3413 , G11C16/3431 , G11C8/10 , G11C8/12 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2216/20 , G11C7/18 , G11C8/00
摘要： A flash memory address decoder includes a plurality of voltage terminals to receive a plurality of voltages, an address terminal to receive a plurality of address signals and a procedure terminal to receive a procedure signal. A block decoder is coupled to the address terminal and configured to decode a portion of the address signals to provide a block select signal. A wordline decoder is coupled to the address terminal and configured to decode a portion of the address signals to provide a wordline select signal. A wordline selector circuit is coupled to the block decoder and the wordline decoder and configured to receive the block select signal and the wordline select signal and to activate addressed wordlines, where the wordline selector is configured to selectively activate addressed wordlines in the flash transistor array and to provide at least two different operational voltages simultaneously on different wordlines in the flash transistor array to accomplish a predetermined procedure responsive to the procedure signal. In one embodiment, a the address decoder includes a latch structure that latches addressed wordlines and provides operational voltages to the wordlines. In another embodiment, the block decoder and wordline decoder include latch structures that latch the block select signal and the wordline select signal to provide operational voltages to the wordline selector. Advantages of the invention include high accuracy and flexibility to read, erase and program the flash memory.
摘要翻译：闪存地址解码器包括多个用于接收多个电压的电压端子，用于接收多个地址信号的地址端子和用于接收过程信号的过程终端。块解码器耦合到地址终端并且被配置为对部分地址信号进行解码以提供块选择信号。字线解码器耦合到地址终端，并且被配置为对地址信号的一部分进行解码以提供字线选择信号。字线选择器电路耦合到块解码器和字线解码器并且被配置为接收块选择信号和字线选择信号并激活寻址字线，其中字线选择器被配置为选择性地激活闪存晶体管阵列中的寻址字线，以在闪光晶体管阵列中的不同字线上同时提供至少两个不同的操作电压，以响应于过程信号来完成预定的过程。在一个实施例中，地址解码器包括锁存寻址字线并向字线提供工作电压的锁存结构。在另一个实施例中，块解码器和字线解码器包括锁存块选择信号和字线选择信号以向字线选择器提供工作电压的锁存结构。本发明的优点包括读取，擦除和编程闪存的高精度和灵活性。

30. 发明授权

US5822252A Flash memory wordline decoder with overerase repair 失效
标题翻译：闪存字幕解码器，过度修复
公开(公告)号：US5822252A
公开(公告)日：1998-10-13
申请号：US676066
申请日：1996-07-05
申请人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Fu-Chang Hsu
IPC分类号： G11C8/08 , G11C8/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/00
CPC分类号： G11C16/3413 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0416 , G11C16/0491 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3418 , G11C16/3427 , G11C16/3431 , G11C8/08 , G11C8/10 , H01L27/115 , G11C16/24 , G11C2211/5642 , G11C2211/5644 , G11C2216/20 , G11C7/1006 , G11C7/18 , G11C8/00 , G11C8/14
摘要： The invention provides a flash memory and decoder with overerase repair that can provide three word line voltages to overcome the overerased problems. The wordline decoder includes a wordline latch that provides a high flexibility of erasing size so that single/multiple sub-wordlines, single/multiple wordlines, single/multiple block, and whole array can be erased simultaneously. An exemplary embodiment of a flash memory wordline decoder that can provide three voltages includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes a plurality of latches coupled to the wordlines and configured to latch the wordlines and to provide one of a plurality of operational voltages on the wordlines to accomplish a predetermined operation responsive to the procedure signal. The plurality of voltage terminals are configured in a way that the high voltage required for erasure or for programming needs not be discharged in verification. Another exemplary embodiment provides a wordline decoder that provides three wordline voltages for verification and repairing, and also for erasure. Advantages of the invention include available full verifications for erasure, repairing and programming, tight cell threshold distribution, high efficiency repairing, no discharging the high voltage cells in verifications, full range verification voltages.
摘要翻译：本发明提供了具有过度修复的闪存和解码器，其可以提供三个字线电压以克服过度存在的问题。字线解码器包括字线锁存器，其提供擦除大小的高灵活性，使得可以同时擦除单个/多个子字线，单个/多个字线，单个/多个块和整个阵列。可以提供三个电压的闪存字线解码器的示例性实施例包括多个用于接收多个电压的电压端子，多个地址端子以接收多个地址信号，接收过程信号的过程终端，以及适于耦合到一组闪存晶体管的多个输出字线。字线解码器电路被配置为对地址信号进行解码，并且包括耦合到字线的多个锁存器，并被配置为锁存字线并且在字线上提供多个工作电压中的一个，以响应于过程信号来完成预定的操作。多个电压端子被配置为在验证中不需要消除擦除或编程所需的高电压。另一示例性实施例提供一种字线解码器，其提供用于验证和修复的三个字线电压，并且还用于擦除。本发明的优点包括用于擦除，修复和编程的可用的完整验证，紧密的单元阈值分布，高效率修复，在验证中不排放高电压单元，全范围验证电压。

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