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21. 发明授权

US08819455B2 Parallelized counter tree walk for low overhead memory replay protection 有权
标题翻译：并行计数器树行走低开销内存重放保护
公开(公告)号：US08819455B2
公开(公告)日：2014-08-26
申请号：US13646105
申请日：2012-10-05
申请人： Siddhartha Chhabra , Uday R. Savagaonkar , David M. Durham , Niranjan L. Cooray , Men Long , Carlos V. Rozas , Alpa T. Narendra Trivedi
发明人： Siddhartha Chhabra , Uday R. Savagaonkar , David M. Durham , Niranjan L. Cooray , Men Long , Carlos V. Rozas , Alpa T. Narendra Trivedi
IPC分类号： G06F11/30 , G06F12/14
CPC分类号： G06F12/1408 , G06F21/71
摘要： A processor includes a memory encryption engine that provides replay and confidentiality protections to a memory region. The memory encryption engine performs low-overhead parallelized tree walks along a counter tree structure. The memory encryption engine upon receiving an incoming read request for the protected memory region, performs a dependency check operation to identify dependency between the incoming read request and an in-process request and to remove the dependency when the in-process request is a read request that is not currently suspended.
摘要翻译：处理器包括为存储器区域提供重放和保密性保护的存储器加密引擎。存储器加密引擎沿着计数器树结构执行低架构并行化的树行走。存储器加密引擎在接收到对受保护的存储器区域的传入读取请求时，执行依赖性检查操作以识别传入的读取请求与进程内请求之间的依赖关系，并且当进程内请求是读取请求时，去除依赖关系目前尚未暂停。

22. 发明申请

US20140208109A1 METHOD AND SYSTEM FOR PROTECTING MEMORY INFORMATION IN A PLATFORM 有权
标题翻译：保护平台内存信息的方法和系统
公开(公告)号：US20140208109A1
公开(公告)日：2014-07-24
申请号：US13976935
申请日：2011-12-28
申请人： Alpa T. Narendra Trivedi , David M. Durham , Men Long , Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas
发明人： Alpa T. Narendra Trivedi , David M. Durham , Men Long , Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas
IPC分类号： H04L29/06
CPC分类号： G06F21/64 , G06F12/1408 , G06F21/78 , G06F21/79 , H04L9/0643 , H04L2209/12
摘要： A method and system to provide an effective, scalable and yet low-cost solution for Confidentiality, Integrity and Replay protection for sensitive information stored in a memory and prevent an attacker from observing and/or modifying the state of the system. In one embodiment of the invention, the system has strong hardware protection for its memory contents via XTS-tweak mode of encryption where the tweak is derived based on “Global and Local Counters”. This scheme offers to enable die-area efficient Replay protection for any sized memory by allowing multiple counter levels and facilitates using small counter-sizes to derive the “tweak” used in the XTS encryption without sacrificing cryptographic strength.
摘要翻译：一种方法和系统，为存储在存储器中的敏感信息提供有效，可扩展且低成本的保密性，完整性和重放保护解决方案，并防止攻击者观察和/或修改系统的状态。在本发明的一个实施例中，系统通过经由XTS调整加密模式对其存储器内容具有强大的硬件保护，其中基于“全局和本地计数器”导出调整。该方案提供了通过允许多个计数器级别为任何大小的存储器提供芯片区域高效的重放保护，并有助于使用小型计数器来导出XTS加密中使用的“调整”，而不会牺牲加密强度。

23. 发明授权

US09092644B2 Method and system for protecting memory information in a platform 有权
标题翻译：保护平台内存信息的方法和系统
公开(公告)号：US09092644B2
公开(公告)日：2015-07-28
申请号：US13976935
申请日：2011-12-28
申请人： Alpa T. Narendra Trivedi , David M. Durham , Men Long , Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas
发明人： Alpa T. Narendra Trivedi , David M. Durham , Men Long , Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas
IPC分类号： G06F21/64 , H04L9/06 , G06F12/14 , G06F21/78 , G06F21/79
CPC分类号： G06F21/64 , G06F12/1408 , G06F21/78 , G06F21/79 , H04L9/0643 , H04L2209/12
摘要： A method and system to provide an effective, scalable and yet low-cost solution for Confidentiality, Integrity and Replay protection for sensitive information stored in a memory and prevent an attacker from observing and/or modifying the state of the system. In one embodiment of the invention, the system has strong hardware protection for its memory contents via XTS-tweak mode of encryption where the tweak is derived based on “Global and Local Counters”. This scheme offers to enable die-area efficient Replay protection for any sized memory by allowing multiple counter levels and facilitates using small counter-sizes to derive the “tweak” used in the XTS encryption without sacrificing cryptographic strength.
摘要翻译：一种方法和系统，为存储在存储器中的敏感信息提供有效，可扩展且低成本的保密性，完整性和重放保护解决方案，并防止攻击者观察和/或修改系统的状态。在本发明的一个实施例中，系统通过经由XTS调整加密模式对其存储器内容具有强大的硬件保护，其中基于“全局和本地计数器”导出调整。该方案提供了通过允许多个计数器级别为任何大小的存储器提供芯片区域高效的重放保护，并有助于使用小型计数器来导出XTS加密中使用的“调整”，而不会牺牲加密强度。

24. 发明申请

US20140123235A1 Allocating Memory Access Control Policies 有权
标题翻译：分配内存访问控制策略
公开(公告)号：US20140123235A1
公开(公告)日：2014-05-01
申请号：US13993421
申请日：2011-12-28
申请人： Prashant Dewan , Jason Martin , Uday R. Savagaonkar , Carlos V. Rozas
发明人： Prashant Dewan , Jason Martin , Uday R. Savagaonkar , Carlos V. Rozas
IPC分类号： G06F21/62
CPC分类号： G06F21/62 , G06F21/53
摘要： Enabling access control caches for co-processors to be charged using a VMX-nonroot instruction. As a result a transition to VMX-root is not needed, saving the cycles involved in such a transition.
摘要翻译：使用VMX-nonroot指令为协处理器启用访问控制高速缓存。因此，不需要转换到VMX-root，从而节省了这种转换所涉及的周期。

25. 发明申请

US20140101461A1 PARALLELIZED COUNTER TREE WALK FOR LOW OVERHEAD MEMORY REPLAY PROTECTION 有权
标题翻译：并行平衡计数器用于低过载存储器重放保护
公开(公告)号：US20140101461A1
公开(公告)日：2014-04-10
申请号：US13646105
申请日：2012-10-05
申请人： Siddhartha Chhabra , Uday R. Savagaonkar , David M. Durham , Niranjan L. Cooray , Men Long , Carlos V. Rozas , Alpa T. Narendra Trivedi
发明人： Siddhartha Chhabra , Uday R. Savagaonkar , David M. Durham , Niranjan L. Cooray , Men Long , Carlos V. Rozas , Alpa T. Narendra Trivedi
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F21/71
摘要： A processor includes a memory encryption engine that provides replay and confidentiality protections to a memory region. The memory encryption engine performs low-overhead parallelized tree walks along a counter tree structure. The memory encryption engine upon receiving an incoming read request for the protected memory region, performs a dependency check operation to identify dependency between the incoming read request and an in-process request and to remove the dependency when the in-process request is a read request that is not currently suspended.
摘要翻译：处理器包括为存储器区域提供重放和保密性保护的存储器加密引擎。存储器加密引擎沿着计数器树结构执行低架构并行化的树行走。存储器加密引擎在接收到对受保护的存储器区域的传入读取请求时，执行依赖性检查操作以识别传入的读取请求与进程内请求之间的依赖关系，并且当进程内请求是读取请求时，去除依赖关系目前尚未暂停。

26. 发明申请

US20140040632A1 LOW-OVERHEAD CRYPTOGRAPHIC METHOD AND APPARATUS FOR PROVIDING MEMORY CONFIDENTIALITY, INTEGRITY AND REPLAY PROTECTION 有权
标题翻译：用于提供记忆保密性，完整性和重复保护的低成本克隆方法和设备
公开(公告)号：US20140040632A1
公开(公告)日：2014-02-06
申请号：US13976930
申请日：2011-12-28
申请人： Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas , Alpa T. Narendra Trivedi , Men Long , David M. Durham
发明人： Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas , Alpa T. Narendra Trivedi , Men Long , David M. Durham
IPC分类号： G06F21/64
CPC分类号： G06F21/64 , G06F12/1408 , G06F21/00 , G06F21/77
摘要： A method and system to provide a low-overhead cryptographic scheme that affords memory confidentiality, integrity and replay-protection by removing the critical read-after-write dependency between the various levels of the cryptographic tree. In one embodiment of the invention, the cryptographic processing of a child node can be pipelined with that of the parent nodes. This parallelization provided by the invention results in an efficient utilization of the cryptographic pipeline, enabling significantly lower performance overheads.
摘要翻译：一种提供低开销加密方案的方法和系统，其通过去除加密树的各个级别之间的关键读后依赖关系来提供内存机密性，完整性和重放保护。在本发明的一个实施例中，子节点的密码处理可以与母节点的密码处理流水线化。由本发明提供的这种并行化导致密码流水线的有效利用，能够显着降低性能开销。

27. 发明授权

US09053346B2 Low-overhead cryptographic method and apparatus for providing memory confidentiality, integrity and replay protection 有权
标题翻译：低开销的加密方法和装置，用于提供内存保密性，完整性和重放保护
公开(公告)号：US09053346B2
公开(公告)日：2015-06-09
申请号：US13976930
申请日：2011-12-28
申请人： Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas , Alpa T. Narendra Trivedi , Men Long , David M. Durham
发明人： Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas , Alpa T. Narendra Trivedi , Men Long , David M. Durham
IPC分类号： G06F12/00 , G06F21/64 , G06F12/14 , G06F21/00 , G06F21/77
CPC分类号： G06F21/64 , G06F12/1408 , G06F21/00 , G06F21/77
摘要： A method and system to provide a low-overhead cryptographic scheme that affords memory confidentiality, integrity and replay-protection by removing the critical read-after-write dependency between the various levels of the cryptographic tree. In one embodiment of the invention, the cryptographic processing of a child node can be pipelined with that of the parent nodes. This parallelization provided by the invention results in an efficient utilization of the cryptographic pipeline, enabling significantly lower performance overheads.
摘要翻译：一种提供低开销加密方案的方法和系统，其通过去除加密树的各个级别之间的关键读后依赖关系来提供内存机密性，完整性和重放保护。在本发明的一个实施例中，子节点的密码处理可以与母节点的密码处理流水线化。由本发明提供的这种并行化导致密码流水线的有效利用，能够显着降低性能开销。

28. 发明申请

US20180114013A1 EXTENDING PACKET PROCESSING TO TRUSTED PROGRAMMABLE AND FIXED-FUNCTION ACCELERATORS 审中-公开
公开(公告)号：US20180114013A1
公开(公告)日：2018-04-26
申请号：US15298419
申请日：2016-10-20
申请人： Kapil Sood , Somnath Chakrabarti , Wei Shen , Carlos V. Rozas , Mona Vij , Vincent R. Scarlata
发明人： Kapil Sood , Somnath Chakrabarti , Wei Shen , Carlos V. Rozas , Mona Vij , Vincent R. Scarlata
IPC分类号： G06F21/53 , G06F12/14 , G06F21/57 , G06F21/44 , G06F9/455 , G06F9/445
CPC分类号： G06F21/53 , G06F8/61 , G06F9/45558 , G06F12/1408 , G06F21/44 , G06F21/572 , G06F21/606 , G06F2009/45587 , G06F2212/1052 , G06F2212/152 , G06F2212/402
摘要： Methods and apparatus for extending packet processing to trusted programmable and fixed-function accelerators. Secure enclaves are created in system memory of a compute platform, wherein software code external from a secure enclave cannot access code or data within a secure enclave, and software code in a secure enclave can access code and data both within the secure enclave and external to the secure enclave. Software code for implementing packet processing operations is installed in the secure enclaves. The compute platform further includes one or more hardware-based accelerators that are used by the software to offload packet processing operations. The accelerators are configured to read packet data from input queues, process the data, and output processed data to output queues, wherein the input and output queues are located in encrypted portions of memory that may be in a secure enclave or external to the secure enclaves. Tokens are used by accelerators to validate access to memory in secure enclaves, and used by both accelerators and secure enclaves to access encrypted memory external to secure enclaves.

29. 发明授权

US07587595B2 Method and apparatus for providing software-based security coprocessors 有权
标题翻译：用于提供基于软件的安全协处理器的方法和装置
公开(公告)号：US07587595B2
公开(公告)日：2009-09-08
申请号：US11171133
申请日：2005-06-29
申请人： Vincent R. Scarlata , Carlos V. Rozas
发明人： Vincent R. Scarlata , Carlos V. Rozas
IPC分类号： H04L9/00
CPC分类号： G06F21/72 , G06F21/53 , G06F21/552 , G06F21/577 , G06F21/602 , G06F21/74 , G06F21/79 , G06F2221/2103 , G06F2221/2105 , G06F2221/2149
摘要： A virtual security coprocessor framework supports creation of at least one device model to emulate a predetermined cryptographic coprocessor. In one embodiment, the virtual security coprocessor framework uses a cryptographic coprocessor in a processing system to create an instance of the device model (DM) in the processing system. The DM may be based at least in part on a predetermined device model design. The DM may emulate the predetermined cryptographic coprocessor in accordance with the control logic of the device model design. In one embodiment, the virtual security coprocessor framework uses a physical trusted platform module (TPM) in a processing system to support one or more virtual TPMs (vTPMs) for one or more virtual machines (VMs) in the processing system. Other embodiments are described and claimed.
摘要翻译：虚拟安全协处理器框架支持创建至少一个设备模型以模拟预定的密码协处理器。在一个实施例中，虚拟安全协处理器框架在处理系统中使用密码协处理器来在处理系统中创建设备模型（DM）的实例。 DM可以至少部分地基于预定的设备模型设计。 DM可以根据设备模型设计的控制逻辑来模拟预定的密码协处理器。在一个实施例中，虚拟安全协处理器框架使用处理系统中的物理信任平台模块（TPM）来支持处理系统中的一个或多个虚拟机（VM）的一个或多个虚拟TPM（vTPM）。描述和要求保护其他实施例。

30. 发明申请

US20110191574A1 METHOD AND APPARATUS FOR BINDING TPM KEYS TO EXECUTION ENTITIES 有权
标题翻译：用于绑定TPM KEYS执行实体的方法和装置
公开(公告)号：US20110191574A1
公开(公告)日：2011-08-04
申请号：US13016145
申请日：2011-01-28
申请人： Alexander Iliev , Vincent R. Scarlata , Carlos V. Rozas
发明人： Alexander Iliev , Vincent R. Scarlata , Carlos V. Rozas
IPC分类号： G06F15/177 , H04L9/32
CPC分类号： G06F21/57 , G06F21/72 , G06F2221/2141 , H04L9/0897
摘要： A method and apparatus for binding trusted platform module (TPM) keys to execution entities are described. In one embodiment, the method includes the receipt of an authorization request issued by an execution entity for authorization data. According to the authorization request, the execution entity may be measured to generate an entity digest value. Once the entity digest value is generated, a platform reference module may grant the authorization request if the entity digest value verifies that the execution entity is an owner of the key held by the TPM. Accordingly, in one embodiment, a platform reference module, rather than an execution entity, holds the authorization data required by a TPM to use a key owned by the execution entity and held within sealed storage by the TPM. Other embodiments are described and claimed.
摘要翻译：描述了将可信平台模块（TPM）密钥绑定到执行实体的方法和装置。在一个实施例中，该方法包括接收由执行实体发出的授权数据的授权请求。根据授权请求，可以测量执行实体以生成实体摘要值。一旦生成实体摘要值，如果实体摘要值验证执行实体是TPM持有的密钥的所有者，则平台引用模块可以授予授权请求。因此，在一个实施例中，平台参考模块而不是执行实体保存TPM所需的授权数据，以使用由执行实体拥有的密钥并由TPM保存在密封存储器内。描述和要求保护其他实施例。

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